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388 Commits

Author SHA1 Message Date
Chad Rosier 15b2498e88 Dead code. 
llvm-svn: 144888
 2011-11-17 07:24:49 +00:00
Chad Rosier ce619ddfc5 Don't unconditionally set the kill flag. 
rdar://10456186

llvm-svn: 144872
 2011-11-17 01:16:53 +00:00
Chad Rosier 80979b6ea6 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
 2011-11-16 18:39:44 +00:00
Chad Rosier af13d767a2 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jay Foad 0745e645e0 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Chad Rosier 057b6d3476 Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Chad Rosier ab7223e99a Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier 45110fdf8d Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Chad Rosier adfd200bcb Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Chad Rosier 2a1df883d0 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Chad Rosier 1198d894d0 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier a476e391f1 Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier 5196efdf36 Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00
Chad Rosier c8cfd3a8fb Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Chad Rosier a7ebc5617d Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Chad Rosier e19b0a9eb8 Rename variables to avoid confusion. No functionallity change intended. 
llvm-svn: 144377
 2011-11-11 06:27:41 +00:00
Chad Rosier 7ddd63ce4e Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00
Chad Rosier 023ede5649 When loading a value, treat an i1 as an i8. 
llvm-svn: 144356
 2011-11-11 02:38:59 +00:00
Chad Rosier 2a3503e061 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Chad Rosier d1762e00e2 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Chad Rosier 3fbd094ad9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Chad Rosier 2f27fab6ed The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

llvm-svn: 144213
 2011-11-09 21:30:12 +00:00
Chad Rosier 595d419427 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
 2011-11-09 03:22:02 +00:00
Chad Rosier 0439cfc41f ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

llvm-svn: 144122
 2011-11-08 21:12:00 +00:00
Chad Rosier 5de1bea5c9 Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Chad Rosier d0191a53c9 Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
 2011-11-05 20:16:15 +00:00
Chad Rosier 5b8fdd7b62 Cannot create a result register for non-legal types. 
llvm-svn: 143749
 2011-11-04 23:45:39 +00:00
Chad Rosier e8b8b77307 When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit 
in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).

llvm-svn: 143743
 2011-11-04 23:09:49 +00:00
Chad Rosier 67f96887aa Enable support for materializing i1, i8, and i16 integers via move immediate. 
llvm-svn: 143739
 2011-11-04 22:29:00 +00:00
Chad Rosier 8a98ec4d4b Indentation. 
llvm-svn: 143670
 2011-11-04 00:58:10 +00:00
Chad Rosier f3e73ad5da Add fast-isel support for returning i1, i8, and i16. 
llvm-svn: 143669
 2011-11-04 00:50:21 +00:00
Chad Rosier bf5f4bec1a Add support for sign-extending non-legal types in SelectSIToFP(). 
llvm-svn: 143603
 2011-11-03 02:04:59 +00:00
Chad Rosier 9cf803c4bf Add support for comparing integer non-legal types. 
llvm-svn: 143559
 2011-11-02 18:08:25 +00:00
Chad Rosier 4489f948a7 Factor out an EmitIntExt function. No functionality change intended. 
llvm-svn: 143547
 2011-11-02 17:20:24 +00:00
Chad Rosier ee7e452571 Factor out a SelectTrunc function. No functionality change intended. 
llvm-svn: 143523
 2011-11-02 00:18:48 +00:00
Chad Rosier d24e7e1d9b A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00
Chad Rosier a486f44733 Add a TODO comment. FastISel works by parsing each basic block from the bottom 
up.  Thus, improving the support for compares is goodness because it increases
the number of terminator instructions we can handle.  This creates many more 
opportunities for target specific fast-isel.

llvm-svn: 143079
 2011-10-26 23:34:37 +00:00
Chad Rosier 78127d31f3 Factor a little more code into EmitCmp, which should have been done in the first 
place.  No functional change intended.

llvm-svn: 143078
 2011-10-26 23:25:44 +00:00
Chad Rosier eafbf3faa9 Use EmitCmp in SelectBranch. No functional change intended. 
llvm-svn: 143076
 2011-10-26 23:17:28 +00:00
Chad Rosier 59a201950b Factor out an EmitCmp function that can be used by both SelectCmp and 
SelectBranch.  No functional change intended.

llvm-svn: 143072
 2011-10-26 22:47:55 +00:00
Chad Rosier b522550ce5 Add a few FIXME comments. 
llvm-svn: 142299
 2011-10-17 22:54:23 +00:00
Bill Wendling 7753d66468 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Jim Grosbach efc761a1eb ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Jim Grosbach e7e2aca322 Tidy up a few 80 column violations. 
llvm-svn: 139636
 2011-09-13 20:30:37 +00:00
Eli Friedman f3dd6da7a8 Don't fast-isel for atomic load/store; some cases require extra handling missing from fast-isel. 
llvm-svn: 139044
 2011-09-02 22:33:24 +00:00
Chad Rosier 17847ae757 Fixup for functions that return a bool. 
llvm-svn: 138918
 2011-08-31 23:49:05 +00:00
Jim Grosbach 50b0f6669c [SU]XT[BH] are only available on ARMv6 and up. 
llvm-svn: 138373
 2011-08-23 20:53:08 +00:00
Jim Grosbach 8b31ef50c0 ARM extend instructions simplification. 
Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.

llvm-svn: 136225
 2011-07-27 16:47:19 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target. 
llvm-svn: 135636
 2011-07-20 23:34:39 +00:00
Chris Lattner 229907cd11 land David Blaikie's patch to de-constify Type, with a few tweaks. 
llvm-svn: 135375
 2011-07-18 04:54:35 +00:00
Evan Cheng 194c3dc01f Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. 
llvm-svn: 134030
 2011-06-28 21:14:33 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
 2011-06-28 19:10:37 +00:00
Eric Christopher 0713a9d8fc Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965

llvm-svn: 132763
 2011-06-08 23:55:35 +00:00
Eli Friedman 86585798af Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. 
rdar://9431157

llvm-svn: 132522
 2011-06-03 01:13:19 +00:00
Cameron Zwarich 6528a54946 Fix ARM fast isel to correctly flag memory operands to stores. This fixes 
-verify-machineinstrs failures on several tests.

llvm-svn: 132268
 2011-05-28 20:34:49 +00:00
Eli Friedman fe84bd659c Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076 
llvm-svn: 132194
 2011-05-27 18:02:04 +00:00
Eli Friedman c70355195c Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent. 
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099
 2011-05-25 23:49:02 +00:00
Eli Friedman 5bbb75655b Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values. 
llvm-svn: 132073
 2011-05-25 19:09:45 +00:00
Jim Grosbach 4e983166bc Kill some dead code. 
llvm-svn: 131431
 2011-05-16 22:24:07 +00:00
Eric Christopher 39b56b4b9f Apparently the check for direct calls is unnecessary. 
llvm-svn: 130716
 2011-05-02 20:16:33 +00:00
Eli Friedman 328bad02fa Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns. 
llvm-svn: 130552
 2011-04-29 22:48:03 +00:00
Eric Christopher 7708746c33 Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but 
if it ever did it needs the def machinery.

llvm-svn: 130549
 2011-04-29 22:07:50 +00:00
Eric Christopher 26b8ac4b8c Some cleanup and optimize fallthrough more. 
llvm-svn: 130546
 2011-04-29 21:56:31 +00:00
Eli Friedman 86caced370 Re-committing r130454, which does not in fact break anything. 
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .

llvm-svn: 130539
 2011-04-29 21:22:56 +00:00
Eric Christopher 8d46b47787 Add trunc->branch support, this won't help with clang's i8->i1 truncations 
for bools, but is a start.

llvm-svn: 130534
 2011-04-29 20:02:39 +00:00
Eric Christopher 9ade5e2495 Update comments and checks to match reality. 
llvm-svn: 130464
 2011-04-29 00:07:20 +00:00
Eric Christopher 501d2e2c14 Whitespace. 
llvm-svn: 130463
 2011-04-29 00:03:10 +00:00
Eli Friedman 517728b1ae Revert r130454; apparently this doesn't actually work. 
llvm-svn: 130462
 2011-04-28 23:55:14 +00:00
Eli Friedman e4ecd42926 Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. 
rdar://problem/9338332 .

llvm-svn: 130454
 2011-04-28 23:03:25 +00:00
Eric Christopher 4f012fd0a1 Be more layout aware here and swap the successor and branch condition 
if it means we get a fallthrough.

llvm-svn: 130404
 2011-04-28 16:52:09 +00:00
Stuart Hastings ebddfe60a0 Correct result when a branch condition is live across a block 
boundary.  <rdar://problem/8933028>

llvm-svn: 129634
 2011-04-16 03:31:26 +00:00
Jay Foad 7c14a558fe Don't include Operator.h from InstrTypes.h. 
llvm-svn: 129271
 2011-04-11 09:35:34 +00:00
Eric Christopher b968f4defe Just use BL all the time. It's safer that way. 
Fixes rdar://9184526

llvm-svn: 128869
 2011-04-05 00:39:26 +00:00
Cameron Zwarich 53dd03d537 Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584
 2011-03-30 23:01:21 +00:00
Eric Christopher a5a779ef45 Migrate the fix in r128041 to ARM's fastisel support as well. 
Fixes rdar://9169640 

llvm-svn: 128100
 2011-03-22 19:39:17 +00:00
Eric Christopher 174d872702 Sometimes isPredicable lies to us and tells us we don't need the operands. 
Go ahead and add them on when we might want to use them and let
later passes remove them.

Fixes rdar://9118569

llvm-svn: 127518
 2011-03-12 01:09:29 +00:00
Eric Christopher 919772fd5d Only use blx for external function calls on thumb, these could be fixed 
up by the dynamic linker, but it's better to use the correct instruction
to begin with.

Fixes rdar://9011034

llvm-svn: 126176
 2011-02-22 01:37:10 +00:00
Eric Christopher 331cc5218d Use the incoming VT not the VT of where we're trying to store to determine 
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357
 2011-01-27 05:44:56 +00:00
Jeffrey Yasskin 249fcd4499 Remove unused variables found by gcc-4.6's -Wunused-but-set-variable. 
llvm-svn: 123707
 2011-01-18 00:51:23 +00:00
Evan Cheng dfce83c8f5 Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. 
movw    r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
        movt    r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
        add     r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.

llvm-svn: 123619
 2011-01-17 08:03:18 +00:00
Chris Lattner 1b3f5b9f74 fix some -Wself-assign warnings. 
llvm-svn: 122893
 2011-01-05 18:41:05 +00:00
Eric Christopher c874f6c9ff Arm and thumb call instructions are also in different orders. 
Fixes rdar://8782223

llvm-svn: 122313
 2010-12-21 03:50:43 +00:00
Eric Christopher 347f4c32e8 Don't handle -arm-long-calls in fast isel for now. 
llvm-svn: 121919
 2010-12-15 23:47:29 +00:00
Eric Christopher 119ff7ff04 Refactor load/store handling again. Simplify and make some room for 
reg+reg handling.

llvm-svn: 120526
 2010-12-01 01:40:24 +00:00
Eric Christopher 78b4efb472 Noticed this on inspection, fix and update some comments. 
llvm-svn: 120447
 2010-11-30 19:14:07 +00:00
Eric Christopher 43b0c6d94f Update fastisel for the changes in r120272. 
llvm-svn: 120324
 2010-11-29 21:56:23 +00:00
Wesley Peck 527da1b6e2 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Eric Christopher 0a3c28bd6b Rewrite address handling to use a structure with all the possible address 
mode variables. Handle frame indexes in load/store and allocas again.

llvm-svn: 119912
 2010-11-20 22:38:27 +00:00
Eric Christopher d0aec3bf64 STRH only needs the additional operand, not t2STRH. Also invert conditional 
to match the one from the load emitter above.

llvm-svn: 119911
 2010-11-20 22:01:38 +00:00
Eric Christopher 35e2d7f610 Don't need to save piecemeal now. 
llvm-svn: 119862
 2010-11-19 22:39:56 +00:00
Eric Christopher cee83d6e6b Update comment. 
llvm-svn: 119861
 2010-11-19 22:37:58 +00:00
Eric Christopher 558b61e2d4 Update comment. 
llvm-svn: 119859
 2010-11-19 22:36:41 +00:00
Eric Christopher fef5f315af Refactor address mode handling into a single struct (ala x86), this 
should give allow a wider range of addressing modes.

No functional change.

llvm-svn: 119856
 2010-11-19 22:30:02 +00:00
Jim Grosbach d7a3550a5e Remove hard tabs. 
llvm-svn: 119810
 2010-11-19 18:01:37 +00:00
Eric Christopher 964943780b Recommit this change and remove the failing part of the test - it didn't 
pass in the first place and was masked by earlier failures not warning
and aborting the block.

llvm-svn: 119184
 2010-11-15 21:11:06 +00:00
Eric Christopher 1293c6a23a Temporarily revert this. 
llvm-svn: 118946
 2010-11-12 23:50:48 +00:00
Eric Christopher 49a66f7d71 Make this happen for ARM like x86. Don't entirely bail out when 
an address is in a different block, get it into a register and go
from there.

llvm-svn: 118936
 2010-11-12 22:52:32 +00:00
Eric Christopher 22d0492f34 Fix up a few more spots of addrmode2 (or not) changes that were 
missed. Update some comments accordingly.

Fixes rdar://8652289

llvm-svn: 118888
 2010-11-12 09:48:30 +00:00
Jim Grosbach 68147ee320 Trailing whitespace. 
llvm-svn: 118606
 2010-11-09 19:22:26 +00:00
Eric Christopher 89965d7091 Make sure we have movw on the target before using it. 
Fixes 8559.

llvm-svn: 118333
 2010-11-06 07:53:11 +00:00
Duncan Sands 71049f78ed In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Eric Christopher e4dd7378d0 Optimize generated code for integer materialization a bit. 
llvm-svn: 118192
 2010-11-03 20:21:17 +00:00
Duncan Sands 1462777017 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands f5dda01f33 Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Eric Christopher c63d846ad6 Invert these branches by default, it makes assembly comparisons a little 
easier to read.

llvm-svn: 118148
 2010-11-03 04:29:11 +00:00
Eric Christopher 1e43892e4b Make sure we're only storing a single bit here. 
llvm-svn: 118126
 2010-11-02 23:59:09 +00:00
Eric Christopher b2abb508ae Remove an assert - it's possible to be hit, and we just want to avoid 
handling those cases for now.

llvm-svn: 117996
 2010-11-02 01:24:49 +00:00
Eric Christopher ac746e1b38 Whitespeace 
llvm-svn: 117995
 2010-11-02 01:22:45 +00:00
Eric Christopher e8fccc82e4 No really, no thumb1 for arm fast isel. Also add an informative comment as 
to what someone would need to do to support thumb1.

llvm-svn: 117994
 2010-11-02 01:21:28 +00:00
Eric Christopher 04b0a3e651 Make sure we have a legal type (and simple) before continuing. 
llvm-svn: 117848
 2010-10-30 21:25:26 +00:00
Eric Christopher 5c308f8452 Handle comparison values we already have - this fixes the consumer-typeset 
failure for llvm-gcc on arm fast isel.

llvm-svn: 117710
 2010-10-29 21:08:19 +00:00
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Jim Grosbach 055de2c789 Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Jim Grosbach 5a7c715470 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Eric Christopher c9616f26bd Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Evan Cheng 21abfc9450 Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Eric Christopher 93bbe6599f Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Eric Christopher 2f8637d393 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Eric Christopher b353e4f579 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Eric Christopher 73bc5b0f86 More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Eric Christopher 4ac3ed0219 Custom lower f64 args passed in integer registers. 
llvm-svn: 116977
 2010-10-21 00:01:47 +00:00
Eric Christopher af719ef86b Fix a TODO by removing some unnecesary copies. 
llvm-svn: 116915
 2010-10-20 08:02:24 +00:00
Eric Christopher 7b92c2a9a0 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Eric Christopher 167a700229 Remove the check for invalid calling conventions. Testing shows that they're 
working just fine.

llvm-svn: 116698
 2010-10-18 06:49:12 +00:00
Eric Christopher c103c668ce Lift arg promotion from the X86 backend. This should be unified at some point. 
llvm-svn: 116694
 2010-10-18 02:17:53 +00:00
Eric Christopher a8a9f3c52b Now that we handle all allocas via a non-SP reg offset remove all of the 
special case handling for ARM::SP.

llvm-svn: 116688
 2010-10-17 11:08:44 +00:00
Eric Christopher 730764da62 Allow more load types to be materialized through the allocas. 
llvm-svn: 116683
 2010-10-17 06:07:26 +00:00
Eric Christopher d265b3fcfe Optimize GEP off of intermediate allocas. 
llvm-svn: 116681
 2010-10-17 01:51:42 +00:00
Eric Christopher a0b9c2e9c0 Fix comment. 
llvm-svn: 116680
 2010-10-17 01:42:53 +00:00
Eric Christopher abc3a9d34b Turn on AddOperator folding in GEP. 
llvm-svn: 116679
 2010-10-17 01:41:46 +00:00
Eric Christopher 947e422c46 Use the i12 immediate versions of the load instructions - they're handled 
more in the post-passes.

llvm-svn: 116678
 2010-10-17 01:40:27 +00:00
Eric Christopher c918d550b6 Fix some funky formatting that got through. 
llvm-svn: 116653
 2010-10-16 01:10:35 +00:00
Eric Christopher f410acbbd5 Make sure offset is 0 for load/store register to the stack call. 
llvm-svn: 116640
 2010-10-15 23:07:10 +00:00
Eric Christopher a3e64c1791 Fix else if -> if in store machinery. 
llvm-svn: 116628
 2010-10-15 22:32:37 +00:00
Eric Christopher a9b3901b47 Refactor ARM fast-isel reg + offset to be a base + offset. 
llvm-svn: 116622
 2010-10-15 21:32:12 +00:00
Eric Christopher e4b3d6b379 Expand GEP handling for constant offsets. 
llvm-svn: 116594
 2010-10-15 18:02:07 +00:00
Eric Christopher 21d0c173f4 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.

llvm-svn: 116474
 2010-10-14 09:29:41 +00:00
Jim Grosbach 340cd5174b A few 80 column fixes. 
llvm-svn: 116451
 2010-10-13 23:34:31 +00:00
Eric Christopher ef83e21b57 Update comment. 
llvm-svn: 116438
 2010-10-13 21:41:51 +00:00
Eric Christopher dd0821e7ff Start handling more global variables. 
llvm-svn: 116401
 2010-10-13 09:11:46 +00:00
Eric Christopher 22e051eef0 Fix thinko in arm fast isel alloca rewrite. 
llvm-svn: 116339
 2010-10-12 21:23:43 +00:00
Eric Christopher 7cd5cda6bb Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher db3bcc9910 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Eric Christopher d42340ecfd Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Eric Christopher 72b91c1765 We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Eric Christopher 71ef1af66b Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
 2010-10-11 21:20:02 +00:00
Eric Christopher e2a0b6841a Found a bug turning this on by default. Disable again for now. 
llvm-svn: 116220
 2010-10-11 20:26:21 +00:00
Eric Christopher 46cc854e5e Fix help text. 
llvm-svn: 116218
 2010-10-11 20:15:02 +00:00
Eric Christopher 5501b7e805 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
 2010-10-11 20:05:22 +00:00
Eric Christopher 2276e87a65 Turn on arm fast isel by default. 
llvm-svn: 116212
 2010-10-11 18:48:18 +00:00
Eric Christopher e1bcb43bb9 Copy and pasteo. 
llvm-svn: 116198
 2010-10-11 08:40:05 +00:00
Eric Christopher 7ac602bc8e Whitespace cleanup in ARM fast isel. 
llvm-svn: 116197
 2010-10-11 08:38:55 +00:00
Eric Christopher eae1b38550 Add srem libcall support to ARM fast isel. 
llvm-svn: 116196
 2010-10-11 08:37:26 +00:00
Eric Christopher e11017c19e Add i8 sdiv support for ARM fast isel. 
llvm-svn: 116195
 2010-10-11 08:31:54 +00:00
Eric Christopher 511aa31965 Implement select handling for ARM fast-isel. 
llvm-svn: 116194
 2010-10-11 08:27:59 +00:00
Eric Christopher 548587c31c Fix the store part of this as well. Fixes smg2000. 
llvm-svn: 116123
 2010-10-08 23:52:16 +00:00
Eric Christopher 15bc2438d9 Move to thumb2 loads, fixes a problem with incoming registers 
as thumb1.

Fixes lencod.

llvm-svn: 116027
 2010-10-08 01:13:17 +00:00
Eric Christopher 3e1e447ca2 Remember to promote load/store types for stack to register size. 
llvm-svn: 115984
 2010-10-07 21:40:18 +00:00
Eric Christopher a2583ea9f2 Use the correct register class for load instructions - fixes 
compilation of MultiSource/Benchmarks/Bullet.

llvm-svn: 115907
 2010-10-07 05:50:44 +00:00
Eric Christopher 76a9752d45 Use the correct register class here. 
llvm-svn: 115906
 2010-10-07 05:39:19 +00:00
Eric Christopher a98be90efe Use the thumb2 conditional move instruction. 
llvm-svn: 115905
 2010-10-07 05:31:49 +00:00
Eric Christopher 6d74673366 Remove in-progress assertion, add TODO. 
llvm-svn: 115904
 2010-10-07 05:14:08 +00:00
Eric Christopher b9f2d50d5f Comment out fastisel debugging message. 
llvm-svn: 115717
 2010-10-05 23:50:58 +00:00
Eric Christopher 8cfc459274 Random cleanup and make the intermediate register in fptosi a 
32-bit fp reg, not 64-bit.

Fixes SingleSource.

llvm-svn: 115711
 2010-10-05 23:13:24 +00:00
Eric Christopher 7787f79f21 Start on lowering global addresses. 
llvm-svn: 115390
 2010-10-02 00:32:44 +00:00
Eric Christopher 83a5ec8fe0 Stub out constant GV handling, fixes C++ eh tests. 
llvm-svn: 115375
 2010-10-01 23:24:42 +00:00
Eric Christopher 9d0136274b Direct calls only for arm fast isel for now. 
llvm-svn: 115350
 2010-10-01 21:33:12 +00:00
Eric Christopher 6080da7a79 Fix thinko on store instructions. Fixes test_indvars failure. 
llvm-svn: 115342
 2010-10-01 20:46:04 +00:00
Eric Christopher c1e209d40e Implement double return values in calls. Fixes 
SingleSource/Regression/C/casts.c.

llvm-svn: 115246
 2010-10-01 00:00:11 +00:00
Eric Christopher 56094ff402 Movement and cleanup. 
llvm-svn: 115225
 2010-09-30 22:34:19 +00:00
Eric Christopher 78f8d4eaf0 Start of generalized call support for ARM fast isel. 
llvm-svn: 115203
 2010-09-30 20:49:44 +00:00
Eric Christopher 7939806ecc Refactor arm fast isel libcall handling so that pieces can be used 
for generic call handling.

llvm-svn: 115105
 2010-09-29 23:11:09 +00:00
Eric Christopher b024be3162 Add a convenience variable so I'm not chasing all over looking for 
a context.

llvm-svn: 115094
 2010-09-29 22:24:45 +00:00
Eric Christopher 3a7e8cd6bd Rework comparison handling to set a register on true/false. This avoids 
problems with phi-nodes in blocks that have hard and not virtual registers.

Accordingly update branch handling to compensate.

llvm-svn: 115013
 2010-09-29 01:14:47 +00:00
Eric Christopher edd4b600f3 Remove unnecessary set ahead of time. 
llvm-svn: 115011
 2010-09-29 00:50:57 +00:00
Eric Christopher 2c8e7f421c Remove assert, add comment. 
llvm-svn: 115009
 2010-09-29 00:49:09 +00:00
Eric Christopher a86a6d2fed 32-bit constant ints only for now. 
llvm-svn: 115001
 2010-09-28 22:47:54 +00:00
Eric Christopher 953b1afd5f Integer materialization needed the same thinko change. 
llvm-svn: 114994
 2010-09-28 21:55:34 +00:00
Eric Christopher 7990df1ae2 Rework builtin handling and call setup. The builtin handling 
now takes a libcall operand, sets up the arguments correctly and
handles stack adjustments.

llvm-svn: 114934
 2010-09-28 01:21:42 +00:00
Eric Christopher 6f98bfd870 Fix fp constant loads to have a destination register. 
llvm-svn: 114930
 2010-09-28 00:35:09 +00:00
Eric Christopher 0720611e3a Insert missing coherency in comment. Add a quick check for hardware 
divide support also.

llvm-svn: 114813
 2010-09-27 06:08:12 +00:00
Eric Christopher 29ab6d1f82 Mass rename for Jim. 
llvm-svn: 114812
 2010-09-27 06:02:23 +00:00
Eric Christopher a6ba082cb6 Thumb opcodes for thumb calls. 
llvm-svn: 114263
 2010-09-18 02:32:38 +00:00
Eric Christopher aef6499bf1 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.

llvm-svn: 114256
 2010-09-18 01:59:37 +00:00
Eric Christopher 30f2300ed2 Floating point stores have a 3rd addressing mode type. 
llvm-svn: 114254
 2010-09-18 01:23:38 +00:00
Eric Christopher 2ccc1aa696 Rework arm fast isel branch and compare code. 
llvm-svn: 114226
 2010-09-17 22:28:18 +00:00
Eric Christopher 8b9126694d Emit libcalls for SDIV, this requires some call infrastructure 
that needs to be shared a bit more widely around.

llvm-svn: 113886
 2010-09-14 23:03:37 +00:00
Eric Christopher 72497e5d90 Start sketching out ARM fast-isel calls. 
llvm-svn: 113662
 2010-09-10 23:18:12 +00:00
Eric Christopher cc766a20d3 For consistency. 
llvm-svn: 113659
 2010-09-10 23:10:30 +00:00
Eric Christopher 712bd0a604 Fix build error. 
llvm-svn: 113566
 2010-09-10 00:35:09 +00:00
Eric Christopher 860fc9370f Update comments, reorganize some code, rename variables to be 
more clear.  No functional change.

llvm-svn: 113565
 2010-09-10 00:34:35 +00:00
Eric Christopher 22fd29a94a 64-bit fp loads can come straight out of the constant pool, not as 
bad as I'd thought.

llvm-svn: 113561
 2010-09-09 23:50:00 +00:00
Eric Christopher 4bd7047324 SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move 
some data around and implement a couple of move routines to do this.

llvm-svn: 113546
 2010-09-09 21:44:45 +00:00
Eric Christopher 2cbe0fd956 New "move to fp reg" routine. Use it. 
llvm-svn: 113537
 2010-09-09 20:49:25 +00:00
Eric Christopher 82b05d7206 "Strike that, reverse it." -- Mr. Wonka. 
Truncate when truncating, extend when extending.

llvm-svn: 113536
 2010-09-09 20:36:19 +00:00
Eric Christopher 5903c0be2a Add FPTrunc, fix some bugs where I forgot to update the value map. 
llvm-svn: 113533
 2010-09-09 20:26:31 +00:00
Eric Christopher 6e3eeba4d9 Basic FP->Int, Int->FP conversions. 
llvm-svn: 113523
 2010-09-09 18:54:59 +00:00
Eric Christopher 2ff757d422 Nuke whitespace and fix some indenting. 
llvm-svn: 113463
 2010-09-09 01:06:51 +00:00
Eric Christopher bd3d121641 Handle 64-bit floating point binops as well. 
llvm-svn: 113461
 2010-09-09 01:02:03 +00:00