Commit Graph

6 Commits

Author SHA1 Message Date
QingShan Zhang f8eabd6d01 [Power9] Add addi post-ra scheduling heuristic
The instruction addi is usually used to post increase the loop indvar, which looks like this:

label_X:
 load x, base(i)
 ...
 y = op x
 ...
 i = addi i, 1
 goto label_X

However, for PowerPC, if there are too many vsx instructions that between y = op x and  i = addi i, 1,
it will use all the hw resource that block the execution of i = addi, i, 1, which result in the stall
of the load instruction in next iteration. So, a heuristic is added to move the addi as early as possible
to have the load hide the latency of vsx instructions, if other heuristic didn't apply to avoid the starve.

Reviewed By: jji

Differential Revision: https://reviews.llvm.org/D80269
2020-06-08 01:31:07 +00:00
Nemanja Ivanovic f2c8f3b181 [PowerPC] Turn on CR-Logical reducer pass
This re-commits r375152 which was pulled in r375233 because it broke
the EXPENSIVE_CHECKS bot on Windows.

The reason for the failure was a bug in the pass that the commit turned
on by default. This patch fixes that bug and turns the pass back on.
This patch has been verified on the buildbot that originally failed
thanks to Simon Pilgrim.

Differential revision: https://reviews.llvm.org/D52431

llvm-svn: 375497
2019-10-22 12:20:38 +00:00
Simon Pilgrim 0a803dd822 [PowerPC] Regenerate test for D52431
llvm-svn: 375435
2019-10-21 17:45:51 +00:00
Nemanja Ivanovic dd7021d466 Revert r375152 as it is causing failures on EXPENSIVE_CHECKS bot
llvm-svn: 375233
2019-10-18 13:38:46 +00:00
Nemanja Ivanovic 8a3d7c9cbd [PowerPC] Turn on CR-Logical reducer pass
Quite a while ago, we implemented a pass that will reduce the number of
CR-logical operations we emit. It does so by converting a CR-logical operation
into a branch. We have kept this off by default because it seemed to cause a
significant regression with one benchmark.
However, that regression turned out to be due to a completely unrelated
reason - AADB introducing a self-copy that is a priority-setting nop and it was
just exacerbated by this pass.

Now that we understand the reason for the only degradation, we can turn this
pass on by default. We have long since fixed the cause for the degradation.

Differential revision: https://reviews.llvm.org/D52431

llvm-svn: 375152
2019-10-17 18:24:28 +00:00
Chen Zheng 469f30abab [PowerPC] Hardware Loop branch instruction's condition may not be icmp.
This fixes pr42492.
Differential Revision: https://reviews.llvm.org/D64124

llvm-svn: 365104
2019-07-04 01:51:47 +00:00