5 Commits

Author	SHA1	Message	Date
David Green	eecba95067	[ARM] Replace arm vendor with none. NFC	2020-04-22 18:19:35 +01:00
Sam Parker	e3a4a13fcc	[ARM][LowOverheadLoops] Enable by default ... The code is now in a good enough state to pass the bunch of tests that I have run (after fixing the bugs), so let's enable it by default. Differential Revision: https://reviews.llvm.org/D65277 llvm-svn: 367297	2019-07-30 08:14:28 +00:00
Sam Parker	3d42959dd8	Revert rL363156. ... The patch was to fix buildbots, but rL363157 should now be fixing it in a cleaner way. llvm-svn: 363174	2019-06-12 15:28:00 +00:00
Sam Parker	ece316b56a	Attempt to fix non-Arm buildbots ... Adding REQUIRES: arm to failing tests llvm-svn: 363156	2019-06-12 12:47:35 +00:00
Sam Parker	757ac02dc8	[ARM] Implement TTI::isHardwareLoopProfitable ... Implement the backend target hook to drive the HardwareLoops pass. The low-overhead branch extension for Arm M-class cores is flexible enough that we don't have to ensure correctness at this point, except checking that the loop counter variable can be stored in LR - a 32-bit register. For it to be profitable, we want to avoid loops that contain function calls, or any other instruction that alters the PC. This implementation uses TargetLoweringInfo, to query type and operation actions, looks at intrinsic calls and also performs some manual checks for remainder/division and FP operations. I think this should be a good base to start and extra details can be filled out later. Differential Revision: https://reviews.llvm.org/D62907 llvm-svn: 363149	2019-06-12 12:00:42 +00:00