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63 Commits

Author SHA1 Message Date
Alexandros Lamprineas 1bab191f25 [MC layer][AArch64] llvm-mc accepts 4-bit immediate values for 
"msr pan, #imm", while only 1-bit immediate values should be valid.
Changed encoding and decoding for msr pstate instructions.

Differential Revision: http://reviews.llvm.org/D13011

llvm-svn: 249313
 2015-10-05 13:42:31 +00:00
Petr Pavlu 097adfb98c [AArch64] Fix problems in decoding generic MSR instructions 
Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174

llvm-svn: 242276
 2015-07-15 08:10:30 +00:00
Javed Absar e1c7dc3ee2 ARM]: Add support for MMFR4_EL1 in assembler 
This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler.
This register provides information about the implemented memory model and memory management support.

llvm-svn: 239302
 2015-06-08 15:01:11 +00:00
Tim Northover 3f3a4d8503 AArch64: fix typo in SMIN far atomics and add tests 
llvm-svn: 238858
 2015-06-02 18:37:20 +00:00
Vladimir Sukharev 5f6f60d942 [AArch64] Add v8.1a atomic instructions 
Patch by: Tom Coxon

Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8501

llvm-svn: 238818
 2015-06-02 10:58:41 +00:00
Tim Northover 03b99f66d7 AArch64: add BFC alias for the BFI/BFM instructions. 
Unlike 32-bit ARM, AArch64 can use wzr/xzr to implement this without the need
for a separate instruction.

rdar://18679590

llvm-svn: 236245
 2015-04-30 18:28:58 +00:00
Vladimir Sukharev bad1d1dc02 [AArch64] LORID_EL1 register must be treated as read-only 
Patch by: John Brawn

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9105

llvm-svn: 235314
 2015-04-20 16:54:37 +00:00
Vladimir Sukharev 6334cf3d69 [AArch64] Add v8.1a "Virtualization Host Extensions" 
Reviewers: t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8500

Patch by: Tom Coxon

llvm-svn: 235107
 2015-04-16 15:38:58 +00:00
Vladimir Sukharev d49cb8fdd7 [AArch64] Add v8.1a "Limited Ordering Regions" extension 
Reviewers: 	t.p.northover

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8499

Patch by: Tom Coxon

llvm-svn: 235105
 2015-04-16 15:30:43 +00:00
Vladimir Sukharev 251ce0c2db [AArch64] Add v8.1a "Privileged Access Never" extension 
Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8498

llvm-svn: 235104
 2015-04-16 15:20:51 +00:00
Bradley Smith b913653b91 [AArch64] Allow non-standard INS/DUP encodings 
The ARMv8 ARMARM states that for these instructions in A64 state:

  "Unspecified bits in "imm5" are ignored but should be set to zero by an assembler.", (imm4 for INS).

Make the disassembler accept any encoding with these ignored bits set to 1.

llvm-svn: 234896
 2015-04-14 15:07:26 +00:00
Vladimir Sukharev 297bf0eae0 [AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension 
Reviewers: t.p.northover, jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8502

llvm-svn: 233693
 2015-03-31 13:15:48 +00:00
Artyom Skrobov 6c8682e2e9 Condition codes AL and NV are invalid in the aliases that use 
inverted condition codes (CINC, CINV, CNEG, CSET, and CSETM).

Matching aliases based on "immediate classes", when disassembling,
wasn't previously supported, hence adding MCOperandPredicate
into class Operand, and implementing the support for it
in AsmWriterEmitter.

The parsing for those aliases was already custom, so just adding
the missing condition into AArch64AsmParser::parseCondCode.

llvm-svn: 210528
 2014-06-10 13:11:35 +00:00
Alp Toker d3d017cf00 Reduce verbiage of lit.local.cfg files 
We can just split targets_to_build in one place and make it immutable.

llvm-svn: 210496
 2014-06-09 22:42:55 +00:00
Artyom Skrobov 0d22e2afe7 Restore getInvertedCondCode() from the phased-out backend, fixing disassembly for NV 
llvm-svn: 209803
 2014-05-29 11:34:50 +00:00
Tim Northover 3b0846e8f7 AArch64/ARM64: move ARM64 into AArch64's place 
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.

"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.

This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.

llvm-svn: 209577
 2014-05-24 12:50:23 +00:00
Tim Northover cc08e1fe1b AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64. 
I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

llvm-svn: 209576
 2014-05-24 12:42:26 +00:00
Tim Northover d8d65a69cf TableGen/ARM64: print aliases even if they have syntax variants. 
To get at least one use of the change (and some actual tests) in with its
commit, I've enabled the AArch64 & ARM64 NEON mov aliases.

llvm-svn: 208867
 2014-05-15 11:16:32 +00:00
Tim Northover ee20caaf82 TableGen: use PrintMethods to print more aliases 
llvm-svn: 208607
 2014-05-12 18:04:06 +00:00
Tim Northover 2d7cacd86b AArch64/ARM64: disable test directory if ARM64 not present 
llvm-svn: 208186
 2014-05-07 10:42:06 +00:00
Tim Northover 618850b6a5 AArch64/ARM64: implement diagnosis of unpredictable loads & stores 
llvm-svn: 208091
 2014-05-06 14:15:14 +00:00
Tim Northover 05017b1f8c AArch64/ARM64: rewrite test to use FileCheck & add ARM64 lines 
llvm-svn: 207754
 2014-05-01 12:30:01 +00:00
Tim Northover 4ec135fa2e AArch64/ARM64: port basic disassembly tests to ARM64. 
llvm-svn: 207753
 2014-05-01 12:29:56 +00:00
Tim Northover 6331d4b975 AArch64: print NEON lists with a space. 
This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.

llvm-svn: 207116
 2014-04-24 14:06:20 +00:00
Kevin Qin 337cfcc83c [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. 
llvm-svn: 195936
 2013-11-29 01:29:16 +00:00
Hao Liu f9f468abee AArch64: Fix a bug about disassembling post-index load single element to 4 vectors 
llvm-svn: 195903
 2013-11-28 01:07:45 +00:00
Chad Rosier 75290c6307 [AArch64] Add support for NEON scalar floating-point absolute difference. 
llvm-svn: 195803
 2013-11-27 01:45:58 +00:00
Chad Rosier 9653d5c989 [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

llvm-svn: 195788
 2013-11-26 22:17:37 +00:00
Hao Liu fbd2b4484c Fixed a bug about disassembling AArch64 post-index load/store single element instructions. 
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

llvm-svn: 195591
 2013-11-25 01:53:26 +00:00
Hao Liu 16edc4675c Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Jiangning Liu bb60ccf355 Implement AArch64 NEON instruction set AdvSIMD (table). 
llvm-svn: 194648
 2013-11-14 01:57:32 +00:00
Chad Rosier 1eb0ecf8ce [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501
 2013-11-12 19:13:08 +00:00
Chad Rosier 35575e737c [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
llvm-svn: 194394
 2013-11-11 18:04:07 +00:00
Jiangning Liu f4226f1d7b Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00
Jiangning Liu a50e22ca4f Implement AArch64 Neon instruction set Bitwise Extract. 
llvm-svn: 194118
 2013-11-06 02:25:49 +00:00
Hao Liu d6b40b51c7 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Chad Rosier 74b65cd811 [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier 20e1f20d69 [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Amara Emerson f80f95fcc7 [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
 2013-10-31 09:32:11 +00:00
Chad Rosier be020d0309 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Chad Rosier fe2f58c8a1 [AArch64] Add support for NEON scalar extract narrow instructions. 
llvm-svn: 192970
 2013-10-18 14:03:24 +00:00
Chad Rosier 37d29173aa [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
 2013-10-17 18:12:29 +00:00
Chad Rosier 846a72539c [AArch64] Add support for NEON scalar negate instruction. 
llvm-svn: 192843
 2013-10-16 21:04:39 +00:00
Chad Rosier 175601d997 [AArch64] Add support for NEON scalar absolute value instruction. 
llvm-svn: 192842
 2013-10-16 21:04:34 +00:00
Chad Rosier abe458d0bf Update comment. 
llvm-svn: 192806
 2013-10-16 16:30:10 +00:00
Chad Rosier 178b1cefc7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
 2013-10-16 16:09:02 +00:00
Chad Rosier 9d51708677 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

llvm-svn: 192733
 2013-10-15 21:18:44 +00:00
Chad Rosier d1f40d760a [AArch64] Add support for NEON scalar integer compare instructions. 
llvm-svn: 192596
 2013-10-14 14:37:20 +00:00
Chad Rosier 9849cc6696 [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
 2013-10-08 22:09:04 +00:00
Chad Rosier f7ed96ef76 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point 
convert instructions.

llvm-svn: 192231
 2013-10-08 20:43:30 +00:00