117f7708c4
Don't try to make a vector of x86mmx; this won't work,
...
and asserts.
llvm-svn: 114843
2010-09-27 17:29:14 +00:00
8118ef8d3d
Fix for test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll crash.
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llvm-svn: 114767
2010-09-24 22:24:05 +00:00
ded5f66813
Get rid of pop_macro warnings on MSVC.
...
llvm-svn: 114750
2010-09-24 19:48:47 +00:00
6b8b2b7312
Revert 114634 for now since buildbot claim it broke Clang self-hosting. I doubt it but it's possible it's exposing another bug somewhere.
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llvm-svn: 114681
2010-09-23 18:32:19 +00:00
57214f533a
Fix VS 2010 build.
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Patch by Nathan Jeffords!
llvm-svn: 114661
2010-09-23 16:59:36 +00:00
b6d175a39d
Follow up to r114630. Do not optimize away unconditional branch following a conditional one.
...
llvm-svn: 114634
2010-09-23 07:18:35 +00:00
79687dda9a
SDISel should not optimize a unconditional branch following a conditional branch
...
when the unconditional branch destination is the fallthrough block. The
canonicalization makes it easier to allow optimizations on DAGs to invert
conditional branches. The branch folding pass (and AnalyzeBranch) will clean up
the unnecessary unconditional branches later.
This is one of the patches leading up to disabling codegen prepare critical edge
splitting.
llvm-svn: 114630
2010-09-23 06:51:55 +00:00
3231d13ddd
A select between a constant and zero, when fed by a bit test, can be efficiently
...
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.
llvm-svn: 114599
2010-09-22 22:58:22 +00:00
c467aa2fa4
Fixed pr20314-2.c failure, added E, F, p constraint letters.
...
llvm-svn: 114490
2010-09-21 22:04:54 +00:00
a9e57e0eff
Rework passing parent pointers into complexpatterns, I forgot
...
that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.
llvm-svn: 114489
2010-09-21 22:00:25 +00:00
99ff76212a
If only user of a vreg is an copy instruction to export copy of vreg out of current basic block then insert DBG_VALUE so that debug value of the variable is also transfered to new vreg.
...
Testcase is in r114476.
This fixes radar 8412415.
llvm-svn: 114478
2010-09-21 20:56:33 +00:00
0bb8b19865
correct this logic.
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llvm-svn: 114474
2010-09-21 20:46:40 +00:00
5e65dfbb97
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
...
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
llvm-svn: 114473
2010-09-21 20:42:50 +00:00
dd83548fea
just like they can opt into getting the root of the pattern being
...
matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.
llvm-svn: 114472
2010-09-21 20:37:12 +00:00
a4f199720d
finish pushing MachinePointerInfo through selectiondags. At this point,
...
I think I've audited all uses, so it should be dependable for address spaces,
and the pointer+offset info should also be accurate when there.
llvm-svn: 114464
2010-09-21 18:58:22 +00:00
676c61db0e
update a bunch of code to use the MachinePointerInfo version of getStore.
...
llvm-svn: 114461
2010-09-21 18:41:36 +00:00
5549d496dd
Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load
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and store intrinsics are represented with MemIntrinsicSDNodes.
llvm-svn: 114454
2010-09-21 17:56:22 +00:00
6963c1f789
eliminate an old SelectionDAG::getTruncStore method, propagating
...
MachinePointerInfo around more.
llvm-svn: 114452
2010-09-21 17:42:31 +00:00
5e39ffd02f
eliminate last SelectionDAG::getLoad old entrypoint, on to stores.
...
llvm-svn: 114450
2010-09-21 17:28:52 +00:00
ea952f05a5
fix the code that infers SV info to be correct when dealing
...
with an indexed load/store that has an offset in the index.
llvm-svn: 114449
2010-09-21 17:24:05 +00:00
3d178ed4d4
propagate MachinePointerInfo through various uses of the old
...
SelectionDAG::getExtLoad overload, and eliminate it.
llvm-svn: 114446
2010-09-21 17:04:51 +00:00
1ffcf527c7
continue MachinePointerInfo'izing, eliminating use of one of the old
...
getLoad overloads.
llvm-svn: 114443
2010-09-21 16:36:31 +00:00
f72c3c08a4
convert dagcombine off the old form of getLoad. This fixes several bugs
...
with SVOffset computation.
llvm-svn: 114442
2010-09-21 16:08:50 +00:00
e32675253f
simplify DAGCombiner::SimplifySelectOps step #2/2.
...
llvm-svn: 114437
2010-09-21 15:58:55 +00:00
254c445e63
substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps.
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no functionality change (step #1 )
llvm-svn: 114436
2010-09-21 15:46:59 +00:00
a35499e2af
a few more trivial updates. This fixes PerformInsertVectorEltInMemory to not
...
pass a completely incorrect SrcValue, which would result in a miscompile with
combiner-aa.
llvm-svn: 114411
2010-09-21 07:32:19 +00:00
2510de2bea
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
...
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
llvm-svn: 114401
2010-09-21 05:40:29 +00:00
bc419ba98f
add overloads for SelectionDAG::getLoad, getStore, getTruncStore that take a
...
MachinePointerInfo. Among other virtues, this doesn't silently truncate the
svoffset to 32-bits.
llvm-svn: 114399
2010-09-21 05:10:45 +00:00
d2d58ada70
simplify interface to SelectionDAG::getMemIntrinsicNode, making it take a MachinePointerInfo
...
llvm-svn: 114397
2010-09-21 04:57:15 +00:00
15d84c460a
chagne interface to SelectionDAG::getAtomic to take a MachinePointerInfo,
...
eliminating some weird "infer a frame address" logic which was dead.
llvm-svn: 114396
2010-09-21 04:53:42 +00:00
3b5dc0cdad
don't implicitly drop the offset of a machinememoperand when legalizing atomics.
...
llvm-svn: 114395
2010-09-21 04:51:11 +00:00
b5f4920979
force clients of MachineFunction::getMachineMemOperand to provide a
...
MachinePointerInfo, propagating the type out a level of API. Remove
the old MachineFunction::getMachineMemOperand impl.
llvm-svn: 114393
2010-09-21 04:46:39 +00:00
272ff94916
When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,
...
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.
This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.
llvm-svn: 114348
2010-09-20 20:39:59 +00:00
7b8d2ae912
Revert r114312 while I sort out some issues.
...
llvm-svn: 114313
2010-09-19 21:01:26 +00:00
ff82f8a35b
Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know,
...
r114268 fixed the last of the blockers to enabling it. I will be monitoring
for failures.
llvm-svn: 114312
2010-09-19 19:51:55 +00:00
b92b13d8a0
Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is
...
NO path to the destination containing side effects, not that SOME path contains no side effects.
In practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".
llvm-svn: 114268
2010-09-18 04:45:14 +00:00
46b96c4ba0
Check bb to ensure that alloca is in separate basic block.
...
This fixes funcargs.exp regression reported by gdb testsuite.
llvm-svn: 113992
2010-09-15 18:13:55 +00:00
da25de8096
If dbg.declare from non-entry block is using alloca from entry block then use offset available in StaticAllocaMap to emit DBG_VALUE. Right now, this has no material impact because varible info also collected using offset table maintained in machine module info.
...
llvm-svn: 113967
2010-09-15 14:48:53 +00:00
e4682fa8e2
Use frame index, if available for byval argument while lowering dbg_declare. Otherwise let getRegForValue() find register for this argument.
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llvm-svn: 113843
2010-09-14 20:29:31 +00:00
93c9b2ea93
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
...
This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
llvm-svn: 113819
2010-09-13 23:59:48 +00:00
79127ab3f5
Silence more warnings. Two more unused variables.
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llvm-svn: 113771
2010-09-13 18:30:57 +00:00
1094c80281
Added skeleton for inline asm multiple alternative constraint support.
...
llvm-svn: 113766
2010-09-13 18:15:37 +00:00
dc38d36ccb
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
...
llvm-svn: 113632
2010-09-10 21:14:25 +00:00
6095d818e5
Add DEBUG message.
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llvm-svn: 113614
2010-09-10 20:32:09 +00:00
bf4070756f
Teach if-converter to be more careful with predicating instructions that would
...
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
llvm-svn: 113570
2010-09-10 01:29:16 +00:00
eeba0c73e5
implement rdar://6653118 - fastisel should fold loads where possible.
...
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
llvm-svn: 113102
2010-09-05 02:18:34 +00:00
3626a8c136
Add a missing check when legalizing a vector extending load. This doesn't
...
solve the root problem, but it corrects the bug in the code I added to
support legalizing in the case where the non-extended type is also legal.
llvm-svn: 112997
2010-09-03 19:20:37 +00:00
3bffd52d78
Detect undef value early and save unnecessary NodeMap query.
...
llvm-svn: 112864
2010-09-02 21:29:42 +00:00
3c9b5f394b
Don't narrow the load and store in a load+twiddle+store sequence unless
...
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
llvm-svn: 112861
2010-09-02 21:18:42 +00:00
98d3edfe2a
Tidy up.
...
llvm-svn: 112858
2010-09-02 21:02:27 +00:00
Dale Johannesen