8c47c3a3b1
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
...
the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
030e002fb9
Set SchedulingForLatency to be the default scheduling preference for all.
...
llvm-svn: 25607
2006-01-25 18:52:42 +00:00
e74795cd70
First part of bug 680:
...
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
1092a02619
Default scheduling preference is SchedulingForLatency.
...
llvm-svn: 25603
2006-01-25 09:15:54 +00:00
ce5066c863
Don't assert on 'select_cc SETUO'
...
llvm-svn: 25423
2006-01-18 19:42:35 +00:00
5bd514d7b0
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
...
llvm-svn: 25334
2006-01-15 09:02:48 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
776c326c96
implement stacksave/stackrestore on PPC
...
llvm-svn: 25277
2006-01-13 17:52:03 +00:00
8e2f52e645
expand unsupported stacksave/stackrestore nodes
...
llvm-svn: 25272
2006-01-13 02:42:53 +00:00
1b8121b227
Add bswap, rotl, and rotr nodes
...
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
llvm-svn: 25222
2006-01-11 21:21:00 +00:00
602dfea79c
Fix calls that need to store values in stack slots, to not copy the stack
...
pointer. This allows us to emit stuff like this:
li r10, 0
stw r10, 56(r1)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
instead of this:
or r2, r1, r1 ;; Extraneous copy.
li r10, 0
stw r10, 56(r2)
or r3, r10, r10
or r4, r10, r10
or r5, r10, r10
or r6, r10, r10
or r7, r10, r10
or r8, r10, r10
or r9, r10, r10
bl L_bar$stub
wowness.
llvm-svn: 25221
2006-01-11 19:55:07 +00:00
66f63f72f3
Dead FP arguments still use an incoming FP reg. This fixes
...
Regression/CodeGen/PowerPC/2006-01-11-darwin-fp-argument.ll, which was
distilled from a miscompilation in 252.eon.
llvm-svn: 25217
2006-01-11 18:21:25 +00:00
347ed8a581
Give PPCISD:: nodes legible names in dumps.
...
llvm-svn: 25166
2006-01-09 23:52:17 +00:00
b87030358d
linkonce symbols have an extra indirection, just like weak ones do. This fixes
...
Prolangs-C++/family and Prolangs-C++/primes.
llvm-svn: 25119
2006-01-06 01:04:03 +00:00
deeafa0f00
Had expand logic backward.
...
llvm-svn: 25105
2006-01-05 01:47:43 +00:00
762e9ec06c
Added initial support for DEBUG_LABEL allowing debug specific labels to be
...
inserted in the code.
llvm-svn: 25104
2006-01-05 01:25:28 +00:00
c2c8a6202f
Remove a fixme
...
llvm-svn: 25045
2005-12-30 00:11:07 +00:00
9aea6e4691
Fix one of the things in the todo file, and get a bit closer to folding
...
constant offsets from statics into the address arithmetic.
llvm-svn: 24999
2005-12-24 01:00:15 +00:00
c46fc2482c
make sure bit_converts are expanded
...
llvm-svn: 24978
2005-12-23 05:13:35 +00:00
f474034432
Simplify some code by using BIT_CONVERT
...
llvm-svn: 24974
2005-12-23 00:59:59 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
...
llvm-svn: 24874
2005-12-20 00:26:01 +00:00
8e6a8af205
Convert load/store over to being pattern matched
...
llvm-svn: 24871
2005-12-19 23:25:09 +00:00
4e56db674c
Add support for TargetConstantPool nodes to the dag isel emitter, and use
...
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
llvm-svn: 24657
2005-12-10 02:36:00 +00:00
fea33f7e64
Use new PPC-specific nodes to represent shifts which require the 6-bit
...
amount handling that PPC provides. These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits. This fixes a miscompilation of crafty with
the new front-end.
llvm-svn: 24615
2005-12-06 02:10:38 +00:00
3713e6b49c
Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.ll
...
llvm-svn: 24547
2005-11-30 20:40:54 +00:00
3e7db9c6d5
Hook up one type, v4f32, to the VR RegisterClass for now.
...
llvm-svn: 24517
2005-11-29 08:17:20 +00:00
9c415364cf
No targets support line number info yet.
...
llvm-svn: 24513
2005-11-29 06:16:21 +00:00
3570cf456b
add an option to generate completely non-pic code, corresponding to what
...
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
llvm-svn: 24399
2005-11-17 18:55:48 +00:00
8f8ed28a64
Fix a bug that resistor on IRC hit where we tried to create token factor
...
nodes of load results, not of their chain results.
llvm-svn: 24398
2005-11-17 18:30:17 +00:00
5aba6ae3b3
Enable global address legalization, fixing a todo and allowing the removal
...
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
llvm-svn: 24397
2005-11-17 18:26:56 +00:00
3648c20472
Use the right accessor to create this node
...
llvm-svn: 24394
2005-11-17 17:51:38 +00:00
595088aa0f
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
...
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
llvm-svn: 24390
2005-11-17 07:30:41 +00:00
b7025749e1
When lowering direct calls, lower them to use a targetglobaladress directly
...
instead of a globaladdress. This has no effect on the generated code at all.
llvm-svn: 24386
2005-11-17 05:56:14 +00:00
f718a9e17b
Fix an assert compiling MallocBench/gs
...
llvm-svn: 24017
2005-10-26 18:01:11 +00:00
762bf809b5
Correctly Expand or Promote FP_TO_UINT based on the capabilities of the
...
machine. This allows us to generate great code for i32 FP_TO_UINT now on
targets with 64 bit extensions.
llvm-svn: 23993
2005-10-25 23:48:36 +00:00
65845a2f7c
Expose the fextend on the DAG instead of doing it in the matcher
...
llvm-svn: 23986
2005-10-25 20:54:57 +00:00
4dd383120f
Invert the TargetLowering flag that controls divide by consant expansion.
...
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
2005-10-21 00:02:42 +00:00
c6f067a8c4
Move the target constant divide optimization up into the dag combiner, so
...
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend. Alpha will probably want this too.
llvm-svn: 23835
2005-10-20 02:15:44 +00:00
78afac2ddd
Add the ability to lower return instructions to TargetLowering. This
...
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
2005-10-18 23:23:37 +00:00
e74dfbb9ce
Do the right thing and enable 64 bit regs under the control of a subtarget
...
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
llvm-svn: 23779
2005-10-18 00:56:42 +00:00
0b71e007ef
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
...
purely mechanical.
llvm-svn: 23778
2005-10-18 00:28:58 +00:00
6cca84e43c
More PPC32 -> PPC changes, as well as merging some classes that were
...
redundant after the change.
llvm-svn: 23759
2005-10-16 05:39:50 +00:00
6f3b954662
Rename PPC32*.h to PPC*.h
...
This completes the grand PPC file renaming
llvm-svn: 23745
2005-10-14 23:59:06 +00:00
a17e6c486c
fix an f32/f64 type mismatch
...
llvm-svn: 23587
2005-10-02 06:37:13 +00:00
d3eee1a09b
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
...
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
llvm-svn: 23577
2005-10-01 01:35:02 +00:00
d3ea19b51a
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
...
llvm-svn: 23506
2005-09-28 22:29:58 +00:00
a028e7a39c
Darwin, like many BSD systems, has a setjmp/longjmp which saves the signal mask
...
on setjmp calls and restores it on longjmp calls (both of which require syscalls).
This makes the calls REALLY slow. Use _setjmp/_longjmp instead. This speeds up
hexxagon from 120.31s to 15.68s: from 5.53x slower than GCC to 28% faster than GCC.
llvm-svn: 23482
2005-09-27 22:18:25 +00:00
0f965a615e
Change the arg lowering code to use copyfromreg from vregs associated
...
with incoming arguments instead of the pregs themselves. This fixes
the scheduler from causing problems by moving a copyfromreg for an argument
to after a select_cc node (now it can, and bad things won't happen).
llvm-svn: 23334
2005-09-13 19:33:40 +00:00
aa6cbd90c5
Remove some dead vectors
...
llvm-svn: 23329
2005-09-13 18:47:49 +00:00
4309c3a785
PowerPC cannot truncstore i1 natively
...
llvm-svn: 23304
2005-09-10 00:21:06 +00:00
6095214bf0
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
...
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
llvm-svn: 23250
2005-09-06 22:03:27 +00:00
aa3b1fcc58
Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.
...
Remove the -enable-gpopt option which is subsumed by feature flags.
llvm-svn: 23218
2005-09-02 18:33:05 +00:00
763a3a0fa7
Restore this patch now that the latent bug has been fixed
...
llvm-svn: 23209
2005-09-02 01:24:55 +00:00
06d440f2ee
Revert the previous patch which causes a mysterious regression in toast.
...
llvm-svn: 23207
2005-09-02 00:47:05 +00:00
9ee867b93b
Implement small-arguments.ll:test3 by teaching the DAG optimizer that
...
the results of calls to functions returning small values are properly
sign/zero extended.
llvm-svn: 23198
2005-09-01 23:44:32 +00:00
da2e04c69d
Move FCTIWZ handling out of the instruction selectors and into legalization,
...
getting them out of the business of making stack slots.
llvm-svn: 23180
2005-08-31 21:09:52 +00:00
e675a08e10
Move SHL,SHR i64 -> legalizer
...
llvm-svn: 23178
2005-08-31 20:23:54 +00:00
2f03896a0f
lower sra_parts on the dag, implementing it for the dag isel, and exposing
...
the ops to dag optimization.
llvm-svn: 23176
2005-08-31 19:09:57 +00:00
e3287b85b7
Enable generation of AssertSext and AssertZext in the PPC backend.
...
llvm-svn: 23168
2005-08-31 01:58:39 +00:00
e75b5e63a7
Fix a bug in my patch for legalizing to fsel. It cannot handle seteq/setne,
...
which I failed to include when I moved the code over. This fixes
MallocBench/gs.
llvm-svn: 23140
2005-08-30 00:45:18 +00:00
62b9a5d1f8
Fix some really strange indentation that xcode likes to use.
...
no xcode, this is not right:
if (!foo) break;
X;
llvm-svn: 23138
2005-08-30 00:19:00 +00:00
9b577f108a
implement SELECT_CC fully for the DAG->DAG isel!
...
llvm-svn: 23101
2005-08-26 21:23:58 +00:00
b2854fadda
Make fsel emission work with both the pattern and dag-dag selectors, by
...
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
llvm-svn: 23091
2005-08-26 20:25:03 +00:00
7f1fa8eaef
implement the other half of the select_cc -> fsel lowering, which handles
...
when the RHS of the comparison is 0.0. Turn this on by default.
llvm-svn: 23083
2005-08-26 17:36:52 +00:00
f3d06c6417
add initial support for converting select_cc -> fsel in the legalizer
...
instead of in the backend. This currently handles fsel cases with registers,
but doesn't have the 0.0 and -0.0 optimization enabled yet.
Once this is finished, special hack for fp immediates can go away.
llvm-svn: 23075
2005-08-26 00:52:45 +00:00
65ffd8fbf4
Remove option to make SetCC illegal on PowerPC after long discussion with
...
Chris. This will be accomplished through correctly modeling CR's and
subregs.
llvm-svn: 23056
2005-08-25 20:01:10 +00:00
f3ce09b36e
Ack, typo
...
llvm-svn: 22981
2005-08-23 05:45:10 +00:00
7216ad415b
Add an option to make SetCC illegal as a beta option
...
llvm-svn: 22979
2005-08-23 05:42:36 +00:00
6267b2c97c
Make UINT_TO_FP and SINT_TO_FP use generic expansion.
...
llvm-svn: 22815
2005-08-17 00:40:22 +00:00
79f5ebc7b9
updates for changes in nodes
...
llvm-svn: 22808
2005-08-16 21:58:15 +00:00
371e49515d
Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty
...
fixme from the PowerPC backend. Emit slightly better code for legalizing
select_cc.
llvm-svn: 22805
2005-08-16 19:49:35 +00:00
f22556d3ad
Pull the LLVM -> DAG lowering code out of the pattern selector so that it
...
can be shared with the DAG->DAG selector.
llvm-svn: 22799
2005-08-16 17:14:42 +00:00
Nate Begeman