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184 Commits

Author SHA1 Message Date
Chris Lattner f376c99ea0 rename hasVariableOperands() -> isVariadic(). Add some comments. 
Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.

llvm-svn: 45687
 2008-01-07 05:19:29 +00:00
Chris Lattner fd548c96cc Move M_* flags down in the file. Move SchedClass up in the 
TargetInstrDescriptor class and shrink to 16-bits, saving a 
word in TargetInstrDescriptor.  Add some comments.

llvm-svn: 45686
 2008-01-07 05:06:49 +00:00
Chris Lattner 6f8713decb the name field of instructions is never set to a non-empty string, 
just unconditionally use the def name of the instruction.

llvm-svn: 45684
 2008-01-07 04:57:31 +00:00
Chris Lattner e55e115616 Add predicates methods to TargetOperandInfo, and switch all clients 
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677
 2008-01-07 02:39:19 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner a348f55ec6 Change the 'isStore' inferrer to look for 'SDNPMayStore' 
instead of "ISD::STORE".  This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores).  This allows us to remove
more explicit isStore flags from the .td files.

Finally, add a warning for when a .td file contains an explicit 
isStore and tblgen is able to infer it.

llvm-svn: 45654
 2008-01-06 06:44:58 +00:00
Chris Lattner 89c6566577 set the 'isstore' flag for instructions whose pattern is an 
intrinsic that writes to memory.

llvm-svn: 45650
 2008-01-06 05:36:50 +00:00
Chris Lattner e457fd1e9b remove some old hacky code that tried to infer whether a store 
occured in a pattern, but failed miserably.  The new code works for
any instruction that has a store in its pattern, including all the 
x86 mem op mem instructions.

The only target-independent code that uses this is branch folding,
so this won't change anything in practice.

llvm-svn: 45648
 2008-01-06 02:16:26 +00:00
Chris Lattner 27a4c1515a rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet. 
llvm-svn: 45647
 2008-01-06 01:53:37 +00:00
Chris Lattner 85467a17ae final cleanups. 
llvm-svn: 45644
 2008-01-06 01:21:51 +00:00
Chris Lattner 626b89daa4 further simplifications and cleanup 
llvm-svn: 45643
 2008-01-06 01:20:13 +00:00
Chris Lattner 827efa451f simplify some code 
llvm-svn: 45642
 2008-01-06 01:12:44 +00:00
Chris Lattner e59a3c79e5 split enum emission out from InstrInfoEmitter into it's own tblgen backend. 
llvm-svn: 45640
 2008-01-06 00:49:05 +00:00
Chris Lattner dc3c9050f8 tblgen shouldn't include headers from llvm codegen. 
llvm-svn: 45429
 2007-12-30 00:25:23 +00:00
Chris Lattner 8adcd9f32e remove attributions from utils. 
llvm-svn: 45419
 2007-12-29 20:37:13 +00:00
Bill Wendling cb77f04e1f Add flags to indicate that there are "never" side effects or that there "may be" 
side effects for machine instructions.

llvm-svn: 45022
 2007-12-14 01:48:59 +00:00
Evan Cheng 687567bca5 Oops. Forgot these. 
llvm-svn: 44969
 2007-12-13 00:42:35 +00:00
Owen Anderson 933b5b7e62 Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Evan Cheng c9de9cec18 Added TargetInstrDescriptor::numDefs - num of results. 
llvm-svn: 40709
 2007-08-02 00:20:17 +00:00
Christopher Lamb cde0ee5221 Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 
llvm-svn: 40518
 2007-07-26 07:48:21 +00:00
Evan Cheng 6e3c705d74 Try committing again. Add OptionalDefOperand. Remove clobbersPred. 
llvm-svn: 38498
 2007-07-10 18:05:01 +00:00
Evan Cheng 9835db562f ImmutablePredicateOperand is no more. 
llvm-svn: 37963
 2007-07-06 23:23:38 +00:00
Evan Cheng e32e7fb40d Instructions with ImmutablePredicateOperand aren't really predicable since their predicates are fixed at isel time. 
llvm-svn: 37899
 2007-07-05 07:19:29 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Evan Cheng 452a818c6a Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions. 
llvm-svn: 37465
 2007-06-06 10:14:55 +00:00
Evan Cheng b99726d7a0 Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable without having a PredicateOperand. 
llvm-svn: 37116
 2007-05-16 20:45:24 +00:00
Evan Cheng c0fb94596a Mark all (not just the first) predicate operand M_PREDICATE_OPERAND. 
llvm-svn: 37061
 2007-05-15 01:20:36 +00:00
Evan Cheng 9d7d130835 Recognize target instruction flag 'isReMaterializable'. 
llvm-svn: 35159
 2007-03-19 06:20:37 +00:00
Jim Laskey 214c582002 Files missing from LABEL check in. 
llvm-svn: 33539
 2007-01-26 17:29:20 +00:00
Bill Wendling 9bfb1e1f29 What should be the last unnecessary <iostream>s in the library. 
llvm-svn: 32333
 2006-12-07 22:21:48 +00:00
Evan Cheng 71adba6dce Add opcode to TargetInstrDescriptor. 
llvm-svn: 31804
 2006-11-17 01:46:27 +00:00
Chris Lattner c94f214d22 ADd support for adding constraints to suboperands 
llvm-svn: 31748
 2006-11-15 02:38:17 +00:00
Chris Lattner ba7b3673f9 allow ptr_rc to explicitly appear in an instructions operand list, it doesn't 
have to be a subpart of a complex operand.

llvm-svn: 31618
 2006-11-10 02:01:40 +00:00
Evan Cheng 1698c2999c Remove M_2_ADDR_FLAG. 
llvm-svn: 31583
 2006-11-09 02:22:54 +00:00
Chris Lattner f62138e792 Mark predicate operands as such in operand info. 
llvm-svn: 31483
 2006-11-06 23:53:31 +00:00
Chris Lattner 33f5a51020 simplify the way operand flags and constraints are handled, making it easier 
to extend.

llvm-svn: 31481
 2006-11-06 23:49:51 +00:00
Chris Lattner 8a9c91de33 recognize ppc's blr instruction as predicated 
llvm-svn: 31480
 2006-11-06 21:44:54 +00:00
Evan Cheng 3cb5bf721c Clean up some code. 
llvm-svn: 31451
 2006-11-04 09:40:23 +00:00
Evan Cheng ac79c7c4c0 Add operand constraints to TargetInstrInfo. 
llvm-svn: 31333
 2006-11-01 00:27:05 +00:00
Jim Laskey 4b49c23571 Eliminate data relocations by using NULL instead of global empty list. 
llvm-svn: 29250
 2006-07-21 21:15:20 +00:00
Jim Laskey 4e153f1b91 Use an enumeration to eliminate data relocations. 
llvm-svn: 29249
 2006-07-21 20:57:35 +00:00
Evan Cheng 55772ccfd6 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng d8e2f6ebc1 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Evan Cheng 21c7c23d7e Noop instruction 
llvm-svn: 28241
 2006-05-12 07:47:00 +00:00
Evan Cheng 386fb9b0fd Set isStore of instructions with ISD::TRUNCSTORE root node. 
llvm-svn: 28075
 2006-05-03 02:08:34 +00:00
Chris Lattner 4b177f089e Put instruction names into the first non TargetInstrInfo namespace found. 
llvm-svn: 28043
 2006-05-01 23:46:16 +00:00
Evan Cheng 8e63393bc3 Formating 
llvm-svn: 28036
 2006-05-01 09:30:17 +00:00
Evan Cheng c2ef5e34a8 Mark instructions whose pattern is (store ...) isStore. 
llvm-svn: 28032
 2006-05-01 09:04:20 +00:00
Chris Lattner 778509c844 Don't fill in fields that no longer exist. 
llvm-svn: 27898
 2006-04-20 18:32:22 +00:00
Chris Lattner db2a5f09f1 If we want to emit things in enum order, use getInstructionsByEnumValue to 
get the order, don't compute it ourselves.

Don't emit stuff like (14<<0), emit 14 instead.

Don't attempt to get target properties for builtin instructions.

llvm-svn: 25672
 2006-01-27 01:44:09 +00:00
Duraid Madina 018da4f5ef almost got the HP-UX tester up.. :) 
llvm-svn: 25051
 2005-12-30 14:56:37 +00:00
Chris Lattner 6bc0304c91 Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
 2005-11-19 07:05:57 +00:00
Jim Laskey 802748cd61 Allow itineraries to be passed through the Target Machine. 
llvm-svn: 24139
 2005-11-01 20:06:59 +00:00
Jeff Cohen 9e1784d738 Keep VC++ happy. 
llvm-svn: 24137
 2005-11-01 18:04:06 +00:00
Jim Laskey 0433df136f Emit itinerary class in instruction info. 
llvm-svn: 24122
 2005-10-31 17:16:46 +00:00
Chris Lattner 742606ad30 Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :) 
llvm-svn: 24074
 2005-10-28 22:59:53 +00:00
Chris Lattner 63dc7f569a spell this variable right 
llvm-svn: 23095
 2005-08-26 20:42:52 +00:00
Chris Lattner 3d9fbefbf7 Expose a new flag to TargetInstrInfo 
llvm-svn: 23094
 2005-08-26 20:40:46 +00:00
Chris Lattner c36c9bdb5d add a marker at the end of the instruction enum list 
llvm-svn: 23090
 2005-08-26 20:17:00 +00:00
Chris Lattner 96d0234845 Emit this: 
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };

For operand information, which does not require dynamic (startup-time)
initialization.

llvm-svn: 22931
 2005-08-19 20:29:14 +00:00
Chris Lattner d02bd5bb05 Emit real operand info for instructions. This currently works but is bad 
in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919
 2005-08-19 18:46:26 +00:00
Chris Lattner 220d00109b For now, just emit empty operand info structures. 
llvm-svn: 22910
 2005-08-19 16:57:28 +00:00
Chris Lattner 511ee687e5 now that all of the targets are clean w.r.t. the number of operands for each 
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter

llvm-svn: 22895
 2005-08-19 00:59:49 +00:00
Chris Lattner b015303c5e revert this change, which causes breakage, temporarily 
llvm-svn: 22880
 2005-08-18 22:12:31 +00:00
Chris Lattner 99df668f48 When emitting implicit use/def lists, only emit each unique list once. Though 
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data.  This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.

This should speed up the register allocator as well by reducing the dcache
footprint for this static data.

llvm-svn: 22879
 2005-08-18 21:36:47 +00:00
Chris Lattner 6f52a04fc7 Fill in the numOperands field of the TargetInstrDescriptor struct from the 
.td file.

llvm-svn: 22873
 2005-08-18 19:45:37 +00:00
Misha Brukman 650ba8eb56 Remove trailing whitespace 
llvm-svn: 21428
 2005-04-22 00:00:37 +00:00
Chris Lattner 945e8655dd Refactor code for numbering instructions into CodeGenTarget. 
llvm-svn: 19758
 2005-01-22 18:58:51 +00:00
Chris Lattner 733c82bfbf Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. 
llvm-svn: 19243
 2005-01-02 02:29:04 +00:00
Nate Begeman 996ddbc98e Add support for the isLoad and isStore flags, needed by the instruction scheduler 
llvm-svn: 16554
 2004-09-28 21:01:45 +00:00
Chris Lattner 9b0dfa3c0d Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG 
llvm-svn: 16553
 2004-09-28 18:38:01 +00:00
Chris Lattner c9d99efdd3 Do not #include files into the llvm namespace 
llvm-svn: 15849
 2004-08-17 03:08:28 +00:00
Chris Lattner 29d8ac77e1 Instructions no longer need to have names. 
llvm-svn: 15399
 2004-08-01 08:38:17 +00:00
Chris Lattner c860ecafe1 Add, and start using, the CodeGenInstruction class. This class represents 
an instance of the Instruction tablegen class.

llvm-svn: 15385
 2004-08-01 05:04:00 +00:00
Chris Lattner fce9603387 Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) 
llvm-svn: 15382
 2004-08-01 04:04:35 +00:00
Chris Lattner 6847866400 Finegrainify namespacification 
llvm-svn: 15381
 2004-08-01 03:55:39 +00:00
Chris Lattner fd4558862c Support new flag 
llvm-svn: 15355
 2004-07-31 02:07:26 +00:00
Brian Gaeke 960707c335 Put all LLVM code into the llvm namespace, as per bug 109. 
llvm-svn: 9903
 2003-11-11 22:41:34 +00:00
John Criswell d3032037f1 Added LLVM copyright header. 
llvm-svn: 9305
 2003-10-20 20:20:30 +00:00
Alkis Evlogimenos 5f1f337d95 Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs 
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}

llvm-svn: 8960
 2003-10-08 05:20:08 +00:00
Chris Lattner f5bd1b7a8e Move support/tools/* back into utils 
llvm-svn: 8875
 2003-10-05 19:27:59 +00:00