Commit Graph

23354 Commits

Author SHA1 Message Date
Jyotsna Verma e758da2080 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with
HexagonInstrFormats.td.

llvm-svn: 175537
2013-02-19 18:18:36 +00:00
Benjamin Kramer 1cb826b0ad Clean up HiPE prologue emission a bit and avoid signed arithmetic tricks.
No intended functionality change.

llvm-svn: 175536
2013-02-19 17:32:57 +00:00
Rafael Espindola 1c040b5788 Move LLVM_LIBRARY_VISIBILITY for consistency with what was done to
PPCJITInfo.cpp in r175394.

llvm-svn: 175531
2013-02-19 17:14:33 +00:00
Eli Bendersky 6aa4fc389e Make ARMAsmPrinter pass name more precise and fix comment.
llvm-svn: 175527
2013-02-19 16:47:59 +00:00
Eli Bendersky b0b13b22a3 Make pass name more precise and fix comment.
llvm-svn: 175525
2013-02-19 16:38:32 +00:00
Arnold Schwaighofer e5083442b2 ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.

The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.

radar://13191881

llvm-svn: 175520
2013-02-19 15:27:05 +00:00
Tom Stellard d4409e2cec R600: Add AR_X to the R600_TReg_X register class.
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175519
2013-02-19 15:22:47 +00:00
Tom Stellard a24a516737 R600: Mark all members of the TRegMem register class as reserved
This stops the Machine Verifier from complaining about uses of undefined
physical registers.

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175518
2013-02-19 15:22:45 +00:00
Tom Stellard 8d469edbe3 R600: Fix scheduler crash caused by invalid MachinePointerInfo
Kernel function arguments are lowered to loads from the PARAM_I address
space.  When creating these load instructions, we were initializing
their MachinePointerInfo with an Arguement object that was not attached
to any function.  This was causing the MachineScheduler to crash when
it tried to access the parent of the Arguement.

This has been fixed by initializing the MachinePointerInfo with a
UndefValue instead.

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175517
2013-02-19 15:22:44 +00:00
Tom Stellard 0f965aaf9b R600: Fix tracking of implicit defs in the IndirectAddressing pass
In some cases, we were losing track of live implicit registers which
was creating dead defs and causing the scheduler to produce invalid
code.

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175516
2013-02-19 15:22:42 +00:00
Craig Topper f371e89264 Fix capitalization in comment to match function name.
llvm-svn: 175497
2013-02-19 07:43:59 +00:00
Reed Kotler 3e457f505e Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .

llvm-svn: 175486
2013-02-19 03:56:57 +00:00
Chandler Carruth c2fd56a21d Remove some unused private fields from the AArch64MCCodeEmitter. These
fields were only ever set in the constructor. The create method retains
its consistent interface so that these bits can be re-threaded through
the emitter if they're ever needed.

This was found by the -Wunused-private-field Clang warning.

llvm-svn: 175482
2013-02-19 02:08:14 +00:00
Reed Kotler d82171990f Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
llvm-svn: 175474
2013-02-19 00:20:58 +00:00
Jakub Staszak 1f199a0ef2 Use array_pod_sort instead of std::sort.
llvm-svn: 175472
2013-02-18 23:18:22 +00:00
NAKAMURA Takumi 3a8002f61d X86FrameLowering.cpp: Fixup. Sorry for the breakage.
llvm-svn: 175467
2013-02-18 23:15:21 +00:00
David Blaikie 772d4f75f6 Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.
Also removes some redundant DNI comments on function declarations already
using the macro.

llvm-svn: 175466
2013-02-18 23:11:17 +00:00
NAKAMURA Takumi a614ec7e6f X86FrameLowering.cpp: Fix a warning in -Asserts. [-Wunused-variable]
llvm-svn: 175464
2013-02-18 23:08:49 +00:00
Chad Rosier 441e81287f Remove a useless assert.
llvm-svn: 175463
2013-02-18 22:20:16 +00:00
Chad Rosier f3f8f443e1 [fast-isel] Remove an invalid assert.
If the memcpy has an odd length with an alignment of 2, this would incorrectly
assert on the last 1 byte copy.
rdar://13202135

llvm-svn: 175459
2013-02-18 21:46:28 +00:00
Benjamin Kramer 5c6e653b72 Fix a 32/64 bit incompatibility in the HiPE prologue generation.
llvm-svn: 175458
2013-02-18 21:45:01 +00:00
Benjamin Kramer 53bc37ca2a Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
llvm-svn: 175457
2013-02-18 20:55:12 +00:00
Vincent Lejeune 1ce13f553e R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
llvm-svn: 175446
2013-02-18 14:11:28 +00:00
Vincent Lejeune 685018009b R600: Support for TBO
NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175445
2013-02-18 14:11:19 +00:00
Vincent Lejeune 4c1602b5c9 R600: Increase number of ArrayBase Reg to 32
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175443
2013-02-18 13:48:09 +00:00
Reed Kotler 1460738710 Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
llvm-svn: 175420
2013-02-18 05:43:03 +00:00
Reed Kotler 6879e56dc7 Expand pseudo/macro BteqzT8SltuX16 . There is no test case because
at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.

llvm-svn: 175419
2013-02-18 04:55:38 +00:00
Reed Kotler c40f4e5899 Expand pseudo/macro BteqzT8SltX16.
llvm-svn: 175417
2013-02-18 04:04:26 +00:00
Reed Kotler 7e4bc6067b Expand macro/pseudo BteqzT8CmpX16.
llvm-svn: 175416
2013-02-18 03:06:29 +00:00
Reed Kotler cb37409b92 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.

llvm-svn: 175413
2013-02-18 00:59:04 +00:00
Benjamin Kramer 189fc5819a X86: Add a note.
llvm-svn: 175408
2013-02-17 23:34:14 +00:00
Richard Osborne 53fff94527 [XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.

llvm-svn: 175407
2013-02-17 22:38:05 +00:00
Richard Osborne f5a3ffcba9 [XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.

llvm-svn: 175406
2013-02-17 22:32:41 +00:00
Richard Osborne 2192615d9f [XCore] Add missing u10 / lu10 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175404
2013-02-17 20:44:48 +00:00
Richard Osborne 3814491fb1 [XCore] Add missing u6 / lu6 instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175403
2013-02-17 20:43:17 +00:00
Jakub Staszak 74010cd9c2 Return false instead of 0.
llvm-svn: 175402
2013-02-17 18:35:25 +00:00
Benjamin Kramer a5dce35cba AArch64: Avoid shifts by 64, that's undefined behavior.
No functionality change.

llvm-svn: 175400
2013-02-17 17:55:32 +00:00
Benjamin Kramer de712b788b Make the visibility of LLVMPPCCompilationCallback work with GCC.
GCC warns about the attribute being ignored if it occurs after void*.
There seems to be some kind of incompatibility between clang and gcc here, but
I can't fathom who's right.

void* LLVM_LIBRARY_VISIBILITY foo(); // clang: hidden, gcc: default
LLVM_LIBRARY_VISIBILITY void *bar(); // clang: hidden, gcc: hidden
void LLVM_LIBRARY_VISIBILITY qux();  // clang: hidden, gcc: hidden

llvm-svn: 175394
2013-02-17 14:30:32 +00:00
Reed Kotler 61b474f97d Clean up mips16 td file in preparation for massive pseudo lowering work.
llvm-svn: 175379
2013-02-16 23:39:52 +00:00
Renato Golin b2603ede95 Typo
llvm-svn: 175371
2013-02-16 19:14:59 +00:00
Reed Kotler 188dad0eeb One more try to make this look nice. I have lots of pseudo lowering
as well as 16/32 bit variants to do and so I want this to look nice
when I do it. I've been experimenting with this. No new test cases
are needed.

llvm-svn: 175369
2013-02-16 19:04:29 +00:00
NAKAMURA Takumi f86d12caf0 [msvc x64] Update X86CompilationCallback_Win64.asm corresponding to r175267.
llvm-svn: 175363
2013-02-16 16:04:29 +00:00
NAKAMURA Takumi eddbc713e1 Target/R600/CMakeLists.txt: Prune SILowerLiteralConstants.cpp corresponding to r175354.
llvm-svn: 175361
2013-02-16 15:30:28 +00:00
Jakub Staszak d784d96074 Minor cleanups. No functionality change.
llvm-svn: 175359
2013-02-16 13:34:26 +00:00
Christian Konig b559b079b4 R600/SI: Add pattern to simplify i64 loading
This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175356
2013-02-16 11:28:36 +00:00
Christian Konig a881179ffe R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.

This actually fixes a piglit test on SI.

v2: use correct register class in addRegisterClass,
    set special classes as not allocatable
v3: revert setting special classes as not allocateable

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175355
2013-02-16 11:28:30 +00:00
Christian Konig c756cb9901 R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.

v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
    use VGPR0 in dummy EXP, avoid compiler warning, break
    after encoding the first literal.
v3: correctly use V_ADD_F32_e64

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175354
2013-02-16 11:28:22 +00:00
Christian Konig b9e281a723 R600/SI: replace AllReg_* with [SV]Src_* v2
Mark all the operands that can also have an immediate.

v2: SOFFSET is also an SSrc_32 operand

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175353
2013-02-16 11:28:13 +00:00
Christian Konig 3c3a7bfb06 R600/SI: fix VOPC encoding v2
Previously it only worked because of coincident.

v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
    for the unused SRC2

This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175352
2013-02-16 11:28:07 +00:00
Christian Konig e3cba88714 R600/SI: move *_Helper definitions to SIInstrFormat.td
This is a candidate for the stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175351
2013-02-16 11:28:02 +00:00