Commit Graph

6922 Commits

Author SHA1 Message Date
Eli Bendersky c66b7b2582 Fix typo
llvm-svn: 175530
2013-02-19 17:11:48 +00:00
Benjamin Kramer b3aa2b8497 Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris.
Due to the execution order of doFinalization functions, the GC information were
deleted before AsmPrinter::doFinalization was executed. Thus, the
GCMetadataPrinter::finishAssembly was never called.

The patch fixes that by moving the code of the GCInfoDeleter::doFinalization to
Printer::doFinalization.

llvm-svn: 175528
2013-02-19 16:51:44 +00:00
Arnold Schwaighofer e5083442b2 ARM NEON: Merge a f32 bitcast of a v2i32 extractelt
A vectorized sitfp on doubles will get scalarized to a sequence of an
extract_element of <2 x i32>, a bitcast to f32 and a sitofp.
Due to the the extract_element, and the bitcast we will uneccessarily generate
moves between scalar and vector registers.

The patch fixes this by using a COPY_TO_REGCLASS and a EXTRACT_SUBREG to extract
the element from the vector instead.

radar://13191881

llvm-svn: 175520
2013-02-19 15:27:05 +00:00
Reed Kotler 3e457f505e Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16,
BtnezT8SltiX16, BtnezT8SltiuX16 .

llvm-svn: 175486
2013-02-19 03:56:57 +00:00
Reed Kotler d82171990f Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
llvm-svn: 175474
2013-02-19 00:20:58 +00:00
Chad Rosier f666b761bd Comment out the rdar number.
llvm-svn: 175460
2013-02-18 21:59:15 +00:00
Chad Rosier f3f8f443e1 [fast-isel] Remove an invalid assert.
If the memcpy has an odd length with an alignment of 2, this would incorrectly
assert on the last 1 byte copy.
rdar://13202135

llvm-svn: 175459
2013-02-18 21:46:28 +00:00
Benjamin Kramer 53bc37ca2a Support for HiPE-compatible code emission, patch by Yiannis Tsiouris.
llvm-svn: 175457
2013-02-18 20:55:12 +00:00
Vincent Lejeune 1ce13f553e R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
llvm-svn: 175446
2013-02-18 14:11:28 +00:00
Reed Kotler 1460738710 Expand macro/pseudo instructions BtnezT8SltX16 and BtnezT8SltuX16.
llvm-svn: 175420
2013-02-18 05:43:03 +00:00
Reed Kotler c40f4e5899 Expand pseudo/macro BteqzT8SltX16.
llvm-svn: 175417
2013-02-18 04:04:26 +00:00
Reed Kotler 7e4bc6067b Expand macro/pseudo BteqzT8CmpX16.
llvm-svn: 175416
2013-02-18 03:06:29 +00:00
Reed Kotler cb37409b92 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.

llvm-svn: 175413
2013-02-18 00:59:04 +00:00
Benjamin Kramer fb9ea4e659 Force a cpu for test. It failed on atom due to different scheduling decisions.
llvm-svn: 175401
2013-02-17 18:26:11 +00:00
Jakub Staszak 6a62c29f6b Replace "check:" wth "CHECK:".
Also fix one test by changing "vpermilps" to "vpshufd".

llvm-svn: 175357
2013-02-16 12:16:56 +00:00
Bill Wendling 61375d8953 Reinitialize the ivars in the subtarget so that they can be reset with the new features.
llvm-svn: 175336
2013-02-16 01:36:26 +00:00
Chad Rosier 925c9b499e [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.
If the frame pointer is omitted, and any stack changes occur in the inline
assembly, e.g.: "pusha", then any C local variable or C argument references
will be incorrect.  

I pass no judgement on anyone who would do such a thing. ;)
rdar://13218191

llvm-svn: 175334
2013-02-16 01:25:28 +00:00
Bill Wendling e9434778f7 Temporary revert of 175320.
llvm-svn: 175322
2013-02-15 23:22:32 +00:00
Bill Wendling a060d0efd8 Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.

llvm-svn: 175320
2013-02-15 23:18:01 +00:00
Paul Redmond f29ddfe93f enable SDISel sincos optimization for GNU environments
- add sincos to runtime library if target triple environment is GNU
- added canCombineSinCosLibcall() which checks that sincos is in the RTL and
  if the environment is GNU then unsafe fpmath is enabled (required to
  preserve errno)
- extended sincos-opt lit test

Reviewed by: Hal Finkel

llvm-svn: 175283
2013-02-15 18:45:18 +00:00
Tim Northover 3533ad6bbd AArch64: remove ConstantIsland pass & put literals in separate section.
This implements the review suggestion to simplify the AArch64 backend. If we
later discover that we *really* need the extra complexity of the
ConstantIslands pass for performance reasons it can be resurrected.

llvm-svn: 175258
2013-02-15 09:33:43 +00:00
Tim Northover 5466e36fb5 AArch64: refactor frame handling to use movz/movk for overlarge offsets.
In the near future litpools will be in a different section, which means that
any access to them is at least two instructions. This makes the case for a
movz/movk pair (if total offset <= 32-bits) even more compelling.

llvm-svn: 175257
2013-02-15 09:33:26 +00:00
Reed Kotler f022147790 Fix minor mips16 issues in directives for function prologue. Probably this does
not matter but makes it more gcc compatible which avoids possible subtle
problems. Also, turned back on a disabled check in helloworld.ll. 

llvm-svn: 175237
2013-02-15 01:04:38 +00:00
Nadav Rotem 495b1a43c1 Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.
llvm-svn: 175190
2013-02-14 18:28:52 +00:00
Weiming Zhao c598700788 Re-apply r175088 for bug fix 13622: Add paired register support for
inline asm with 64-bit data on ARM

Update test case to use -mtriple=arm-linux-gnueabi

llvm-svn: 175186
2013-02-14 18:10:21 +00:00
Vincent Lejeune f940fd05bd R600: Do not fold single instruction with more that 3 kcache read
It fixes around 100 tfb piglit tests and 16 glean tests.

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 175183
2013-02-14 16:57:19 +00:00
Kristof Beyls 2efb59a719 Make ARMAsmParser accept the correct alignment specifier syntax in instructions.
The parser will now accept instructions with alignment specifiers written like
    vld1.8  {d16}, [r0:64]
, while also still accepting the incorrect syntax
    vld1.8  {d16}, [r0, :64]

llvm-svn: 175164
2013-02-14 14:46:12 +00:00
Elena Demikhovsky d0a0cc80cd Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).
Added a test.

llvm-svn: 175144
2013-02-14 08:20:26 +00:00
Michel Danzer 51d5eb2f63 R600: Add lit tests for texture sampling instruction selection.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 175138
2013-02-14 07:43:51 +00:00
Andrew Trick 6871e5f4e5 Reapply "s/grep/FileCheck/ in some tests"
This reverts commit fd1335e982bbf93c5f450ed4fd29f9f787435c85.

Use a triple this time.

llvm-svn: 175134
2013-02-14 03:45:08 +00:00
Andrew Trick 836bf1526b Revert "s/grep/FileCheck/ in some tests"
This reverts commit 8b75e6bc35fb3f9c1e788dbd05084c0f4a60a0f3.

The FileCheck tests are not equivalent:

test/CodeGen/X86/tailcall-structret.ll:6:10: error: expected string not found in input
; CHECK: jmp init
         ^
<stdin>:1:2: note: scanning from here
 .section __TEXT,__text,regular,pure_instructions
 ^
<stdin>:13:2: note: possible intended match here
 jmp _init ## TAILCALL
 ^

llvm-svn: 175124
2013-02-14 03:00:57 +00:00
Weiming Zhao 090edf7e67 temporarily revert the patch due to some conflicts
llvm-svn: 175107
2013-02-13 23:24:40 +00:00
Anshuman Dasgupta e96f804eba Hexagon: add support for predicate-GPR copies.
llvm-svn: 175102
2013-02-13 22:56:34 +00:00
Tom Stellard 91da4e9199 R600: Add support for 128-bit parameters
NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175096
2013-02-13 22:05:20 +00:00
Eli Bendersky 3ffeb68dd7 s/grep/FileCheck/ in some tests
llvm-svn: 175093
2013-02-13 22:00:37 +00:00
Eli Bendersky 04553985d7 s/grep/FileCheck/ in some tests
llvm-svn: 175089
2013-02-13 21:46:38 +00:00
Weiming Zhao 0632a4b002 Bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM
llvm-svn: 175088
2013-02-13 21:43:02 +00:00
Chad Rosier da05cf7ba7 [ms-inline asm] Fix up test case for non-Darwin platforms.
llvm-svn: 175087
2013-02-13 21:41:58 +00:00
Jyotsna Verma d92252469e Hexagon: Use absolute addressing mode loads/stores for global+offset
instead of redefining separate instructions for them.

llvm-svn: 175086
2013-02-13 21:38:46 +00:00
Chad Rosier 282edd7caa [ms-inline-asm] Add support for memory references that have non-immediate
displacements.
rdar://12974533

llvm-svn: 175083
2013-02-13 21:33:44 +00:00
Reed Kotler f662cff689 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
David Peixotto 6eecb28d3a PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.

llvm-svn: 175066
2013-02-13 19:21:47 +00:00
Benjamin Kramer 8e2637e2b0 X86: Disable generation of rep;movsl when %esi is used as a base pointer.
This happens when there is both stack realignment and a dynamic alloca in the
function. If we overwrite %esi (rep;movsl uses fixed registers) we'll lose the
base pointer and the next register spill will write into oblivion.

Fixes PR15249 and unbreaks firefox on i386/freebsd. Mozilla uses dynamic allocas
and freebsd a 4 byte stack alignment.

llvm-svn: 175057
2013-02-13 13:40:35 +00:00
Reed Kotler 9cb8e7b9f5 Make jumptables work for -static
llvm-svn: 175044
2013-02-13 08:32:14 +00:00
Elena Demikhovsky 9e0df7cb01 Prevent insertion of "vzeroupper" before call that preserves YMM registers, since a caller uses preserved registers across the call.
llvm-svn: 175043
2013-02-13 08:02:04 +00:00
Eric Christopher 389ee71b0a Check i1 as well as i8 variables for 8 bit registers for x86 inline
assembly.

llvm-svn: 175036
2013-02-13 06:01:05 +00:00
Eric Christopher 2398a9a175 Finish obviously broken thought.
llvm-svn: 175035
2013-02-13 06:01:00 +00:00
Paul Redmond 7e7e3de43d Fix the lit test added in r174972
Patch by: Kevin Schoedel

llvm-svn: 174974
2013-02-12 16:07:27 +00:00
Jyotsna Verma 39f7a2b7a0 Hexagon: Add support to generate predicated absolute addressing mode
instructions.

llvm-svn: 174973
2013-02-12 16:06:23 +00:00
Paul Redmond 288604ed0c PR14562 - Truncation of left shift became undef
DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32))
into (shl i32 v, 32) into undef. To prevent this, check the shift count
against the final result size.

Patch by: Kevin Schoedel
Reviewed by: Nadav Rotem

llvm-svn: 174972
2013-02-12 15:21:21 +00:00