llvm-project

Commit Graph

Author	SHA1	Message	Date
Ana Pazos	10de234905	[RISC-V] Fixed alias for addi x2, x2, 0 A missing check for non-zero immediate in MCOperandPredicate caused c.addi16sp sp, 0 to be selected which is not a valid instruction. llvm-svn: 339381	2018-08-09 20:51:53 +00:00
Alex Bradbury	6a4b5441e4	[RISCV] AsmParser support for the li pseudo instruction The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. The actual expansion to real instructions is similar to the expansion performed by the GNU Assembler. This patch supersedes D41949. Differential Revision: https://reviews.llvm.org/D46118 Patch by Mario Werner. llvm-svn: 334203	2018-06-07 15:35:47 +00:00

Author

SHA1

Message

Date

Ana Pazos

10de234905

[RISC-V] Fixed alias for addi x2, x2, 0

A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.

llvm-svn: 339381

2018-08-09 20:51:53 +00:00

Alex Bradbury

6a4b5441e4

[RISCV] AsmParser support for the li pseudo instruction

The implementation follows the MIPS backend and expands the pseudo instruction 
directly during asm parsing. As the result, only real MC instructions are 
emitted to the MCStreamer. The actual expansion to real instructions is 
similar to the expansion performed by the GNU Assembler.

This patch supersedes D41949.

Differential Revision: https://reviews.llvm.org/D46118
Patch by Mario Werner.

llvm-svn: 334203

2018-06-07 15:35:47 +00:00

2 Commits