25a39094f8
Add debug dumps.
...
llvm-svn: 56178
2008-09-13 01:15:21 +00:00
c5c74f36fd
Eliminate unnecessary instruction formats.
...
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
d1424c4eca
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
...
llvm-svn: 56172
2008-09-12 22:45:55 +00:00
33fa89c6fb
Rewrite address mode 1 code emission routines.
...
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
effb894453
Rename ConstantSDNode::getValue to getZExtValue, for consistency
...
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
llvm-svn: 56159
2008-09-12 16:56:44 +00:00
a7cd7bc353
udpate header comment: s/VP/VFP/
...
llvm-svn: 56126
2008-09-11 21:41:29 +00:00
dd45bc25ac
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
...
llvm-svn: 56119
2008-09-11 20:28:43 +00:00
453564bfba
Fix a bug in ANY_EXTEND handling that was breaking 403.gcc on X86-64 in fast isel.
...
llvm-svn: 56117
2008-09-11 19:44:55 +00:00
58d084c05b
The version of AtomicSDNode::AtomicSDNode used (only) for
...
cmp-and-swap reversed the Cmp and Swap arguments; comments
make it clear this is unintentional. Unfortunately, the
x86 BE had a compensating reversal, which is removed here.
PPC is OK.
From inspection of the Alpha code I think it is OK, but
if somebody has that platform please check it out. I
cannot test on that platform.
llvm-svn: 56091
2008-09-11 03:12:59 +00:00
41baf8b22a
If ISD::ANY_EXTEND fails, try ISD::ZERO_EXTEND and ISD::SIGN_EXTEND before giving up. This fixes 445.gobmk on
...
X86-64 in fast isel.
llvm-svn: 56088
2008-09-11 02:41:37 +00:00
e5ca04e70d
Succumb utterly to compatibility and implement
...
__sync_fetch_and_nand as ANDC, even though that's
not what nand means.
llvm-svn: 56087
2008-09-11 02:15:03 +00:00
bf646f2986
X86FastISel support for double->float and float->double casts.
...
llvm-svn: 56070
2008-09-10 21:02:08 +00:00
39d82f902a
Add X86FastISel support for static allocas, and refences
...
to static allocas. As part of this change, refactor the
address mode code for laods and stores.
llvm-svn: 56066
2008-09-10 20:11:02 +00:00
710c3cf36a
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
...
llvm-svn: 56061
2008-09-10 18:25:29 +00:00
4cc893bab6
Handle new intrinsics with vector arguments.
...
Patch by Paul Redmond.
llvm-svn: 56059
2008-09-10 17:31:40 +00:00
6d6a65310b
Fix name.
...
llvm-svn: 56055
2008-09-10 13:22:10 +00:00
83e45acc25
Add trampoline support for the new FastCC calling
...
convention (not related to recent Ada testsuite
failures).
llvm-svn: 56054
2008-09-10 13:11:09 +00:00
536c399579
Turn off the new FastCC for the moment. It causes
...
a slew of Ada testsuite failures on x86-32 linux.
Seems to be related to the use of float.
llvm-svn: 56053
2008-09-10 13:09:24 +00:00
abb1e7770b
Move the uglier parts of deciding not to emit a
...
UsedDirective for some symbols in llvm.used into
Darwin-specific code. I've decided LessPrivateGlobal
is potentially a useful abstraction and left it in
the target-independent area, with improved comment.
llvm-svn: 56024
2008-09-09 22:29:13 +00:00
1a1140429e
Make safer variant of alias resolution routine to be default
...
llvm-svn: 56005
2008-09-09 20:05:04 +00:00
4fcccd8d66
Mark IMPLICIT_DEF as being rematerializable and cheap-as-a-move.
...
It's already special-cased and treated as rematerializable within
LiveIntervals; this allows it to be handled by other passes
such as TwoAddressInstrctionPass.
llvm-svn: 55999
2008-09-09 18:25:28 +00:00
6acb2219b6
Replace explicit pointer-size constants to TargetData query.
...
No functionality change.
llvm-svn: 55996
2008-09-09 18:22:57 +00:00
1e97901388
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
...
llvm-svn: 55975
2008-09-09 01:26:59 +00:00
f080225490
Fix logic for not emitting no-dead-strip for some
...
objects in llvm.used (thanks Anton). Makes visible
the magic 'l' prefix for symbols on Darwin which are
to be passed through the assembler, then removed at
linktime (previously all references to this had been
hidden in the ObjC FE code, oh well).
llvm-svn: 55973
2008-09-09 01:21:22 +00:00
177eda0505
Reapply 55901: Drop unused variable
...
llvm-svn: 55957
2008-09-08 21:13:33 +00:00
524820fef7
Reapply 55900: We do support EH on x86-64!
...
llvm-svn: 55956
2008-09-08 21:13:08 +00:00
2fd24e7713
Reapply 55899: First draft of EH support on x86/64-linux
...
Now with fix, which prevents subtle codegen bug to trigger on darwin.
No fix for bug though, it's still there.
llvm-svn: 55955
2008-09-08 21:12:47 +00:00
4112634ca6
Reapply blindly reverted 55898: Implement FRAME_TO_ARGS_OFFSET for x86-64
...
llvm-svn: 55954
2008-09-08 21:12:11 +00:00
3871441861
Reverting r55898 as well. This wasn't reverted in the original revert...
...
llvm-svn: 55938
2008-09-08 19:42:32 +00:00
6fe5fe4209
Accidental commit of partial 'stack canaries' code
...
llvm-svn: 55937
2008-09-08 18:12:00 +00:00
99b83712f3
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
llvm-svn: 55928
2008-09-08 17:59:12 +00:00
d172048b59
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
...
llvm-svn: 55925
2008-09-08 17:15:42 +00:00
fd18d630bc
i128 and f80 are implemented for x86-64 now.
...
llvm-svn: 55920
2008-09-08 16:42:56 +00:00
8f658bac2f
Fix copy+pastos in comments.
...
llvm-svn: 55918
2008-09-08 16:31:35 +00:00
4d5b5fe812
Delete an unused variable.
...
llvm-svn: 55915
2008-09-08 16:28:17 +00:00
b55688d27d
Drop unused variable
...
llvm-svn: 55901
2008-09-08 14:22:38 +00:00
0316b797ea
We do support EH on x86-64!
...
llvm-svn: 55900
2008-09-08 14:22:16 +00:00
82b9540046
First draft of EH support on x86/64-linux
...
llvm-svn: 55899
2008-09-08 14:21:53 +00:00
cb0655d626
Implement FRAME_TO_ARGS_OFFSET for x86-64
...
llvm-svn: 55898
2008-09-08 14:21:10 +00:00
6500d1711a
Add support to extend call operands when needed. Enable x86 fastisel call support.
...
llvm-svn: 55891
2008-09-08 06:35:17 +00:00
6c8f55c841
Initial fastisel call support for C, Fast, and X86_FastCall calling conventions. It's meant to handle "simple" calls, i.e. no byval, structret, etc. It doesn't support multi-result returns either.
...
Not yet turned on, it needs to support sext / zext of arguments and result.
llvm-svn: 55882
2008-09-07 09:09:33 +00:00
6f343bd543
Some code clean up.
...
llvm-svn: 55881
2008-09-07 09:07:23 +00:00
b928669409
Handle x86 truncate to i8 with target hook for now.
...
llvm-svn: 55877
2008-09-07 08:47:42 +00:00
d41c7160d0
Fix constant pool loads, and remove broken versions of addConstantPoolReference.
...
llvm-svn: 55868
2008-09-06 01:11:01 +00:00
9519fb3f50
Fix the X86 addConstantPoolReference, which had the operands in the wrong order.
...
llvm-svn: 55867
2008-09-06 00:50:00 +00:00
a9c52c8219
Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x
...
i32>. This is a little messy, but it works.
We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.
llvm-svn: 55864
2008-09-05 23:07:03 +00:00
db06a99239
Fix X86FastISel's shift and select code to reject illegal types.
...
llvm-svn: 55857
2008-09-05 21:27:34 +00:00
e556018dc0
Fix the opcodes used by X86FastISel for shifts and conditional moves.
...
llvm-svn: 55855
2008-09-05 21:13:04 +00:00
f5bc7e57bc
Factor out code that emits load and store instructions.
...
llvm-svn: 55854
2008-09-05 21:00:03 +00:00
ffcc884c77
Rename method.
...
llvm-svn: 55853
2008-09-05 20:49:33 +00:00
7d7a26df65
X86FastISel support for shifts and conditional moves.
...
llvm-svn: 55844
2008-09-05 18:30:08 +00:00
4f0d21592a
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
...
llvm-svn: 55840
2008-09-05 17:24:07 +00:00
09faf81b6c
Check a comparion's operand type for legality before
...
expanding its operands.
llvm-svn: 55820
2008-09-05 01:33:56 +00:00
ffd89d40d2
Fix X86FastISel code for comparisons and conditional branches
...
to check the result of getRegForValue before using it, and
to check for illegal operand types.
llvm-svn: 55819
2008-09-05 01:15:35 +00:00
a5753b31be
X86FastISel support for conditional branches.
...
llvm-svn: 55816
2008-09-05 01:06:14 +00:00
50288e3c99
Add initial support for selecting constant materializations that require constant
...
pool loads on X86 in fast isel. This isn't actually used yet.
llvm-svn: 55814
2008-09-05 00:06:23 +00:00
09fdbcf400
X86FastISel support for ICmpInst and FCmpInst.
...
llvm-svn: 55811
2008-09-04 23:26:51 +00:00
6c94b99c62
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
...
llvm-svn: 55807
2008-09-04 22:59:58 +00:00
b9d5e02811
If function notes say optimize for size, then adjust alignment.
...
llvm-svn: 55794
2008-09-04 21:03:41 +00:00
a79db30d28
Tidy up several unbeseeming casts from pointer to intptr_t.
...
llvm-svn: 55779
2008-09-04 17:05:41 +00:00
b8c7ba228f
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
...
llvm-svn: 55777
2008-09-04 16:48:33 +00:00
634412fe35
Clean up uses of TargetLowering::getTargetMachine.
...
llvm-svn: 55769
2008-09-04 15:39:15 +00:00
4f948bd87a
Add a first attempt at implementing stores for X86 fast isel using target hooks.
...
Dan or Evan, please review.
llvm-svn: 55764
2008-09-04 07:08:58 +00:00
8d8f47d50b
Load from GV stub should be locally CSE'd.
...
llvm-svn: 55763
2008-09-04 06:18:33 +00:00
3152edf474
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
...
llvm-svn: 55756
2008-09-04 01:04:15 +00:00
da2d80688b
Add intrinsics for log, log2, log10, exp, exp2.
...
No functional change (and no FE change to generate them).
llvm-svn: 55753
2008-09-04 00:47:13 +00:00
7bda51f5a4
Create HandlePHINodesInSuccessorBlocksFast, a version of
...
HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.
This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.
llvm-svn: 55746
2008-09-03 23:12:08 +00:00
a41ee2974b
Add X86 target hook to implement load (even from GlobalAddress).
...
llvm-svn: 55693
2008-09-03 06:44:39 +00:00
2175b55dc7
Fix capitalization in #include of FastISel.h. This unbreaks the build on case-sensitive filesystems.
...
llvm-svn: 55687
2008-09-03 02:54:11 +00:00
8f23ec96b0
Unbreak fast isel.
...
llvm-svn: 55685
2008-09-03 01:04:47 +00:00
24422d4928
Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.
...
llvm-svn: 55679
2008-09-03 00:03:49 +00:00
bc69829b22
Fix some bugs in the code sequences for atomics.
...
llvm-svn: 55643
2008-09-02 20:30:23 +00:00
df8cdc3717
Add Mac OS X compatible JIT callback routine.
...
llvm-svn: 55625
2008-09-02 07:49:03 +00:00
3be5b728b1
Revamp ARM JIT.
...
llvm-svn: 55624
2008-09-02 06:52:38 +00:00
34f3a962b0
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
...
llvm-svn: 55623
2008-09-02 06:51:36 +00:00
fa558788e7
Control flow instruction encodings.
...
llvm-svn: 55601
2008-09-01 08:25:56 +00:00
c288cc0572
ldm / stm instruction encodings.
...
llvm-svn: 55599
2008-09-01 07:48:18 +00:00
c37532b24a
AXI2 and AXI3 instruction encodings.
...
llvm-svn: 55598
2008-09-01 07:34:13 +00:00
a282723499
Reorganize instruction formats again; AXI1 encoding.
...
llvm-svn: 55597
2008-09-01 07:19:00 +00:00
169eccc24e
addrmode3 instruction encodings.
...
llvm-svn: 55596
2008-09-01 07:00:14 +00:00
624844b4dd
Reorganize some instruction format definitions. No functionality change.
...
llvm-svn: 55594
2008-09-01 01:51:14 +00:00
cccca875b1
Rest of addrmode2 instruction encodings.
...
llvm-svn: 55593
2008-09-01 01:27:33 +00:00
01fd3f129a
Addr2 word / byte load encodings.
...
llvm-svn: 55591
2008-08-31 19:02:21 +00:00
5b6c931e1f
Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.
...
llvm-svn: 55590
2008-08-31 18:32:16 +00:00
81d6a38434
fix a bunch of 80-col violations
...
llvm-svn: 55588
2008-08-31 15:37:04 +00:00
aebd2662d3
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
...
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
62cf24343c
Expand for ROTR with MVT::i64.
...
Dale, Could you please review this?
llvm-svn: 55581
2008-08-31 02:53:19 +00:00
a719239719
fix some 80-col violations
...
llvm-svn: 55565
2008-08-30 10:09:02 +00:00
b8d588d89c
For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.
...
llvm-svn: 55562
2008-08-30 08:54:22 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
...
llvm-svn: 55558
2008-08-30 02:03:58 +00:00
340d264f52
Add ppc partial-word ATOMIC_CMP_SWAP.
...
llvm-svn: 55554
2008-08-30 00:08:53 +00:00
3fddc7e906
Swap fp comparison operands and change predicate to allow load folding (safely this time).
...
llvm-svn: 55553
2008-08-29 23:22:12 +00:00
f93bc7f755
Use static_cast instead of C style cast.
...
llvm-svn: 55552
2008-08-29 23:21:31 +00:00
b3ed09703c
Backing out 55521. Not safe.
...
llvm-svn: 55548
2008-08-29 22:13:21 +00:00
f0a88d6b2a
Add partial word version of ATOMIC_SWAP.
...
llvm-svn: 55546
2008-08-29 18:29:46 +00:00
0673a8af14
Add initial support for fast isel of instructions that have inputs pinned to physical registers.
...
llvm-svn: 55545
2008-08-29 17:45:56 +00:00
44b2138b9a
TableGen'ing instruction encodings.
...
llvm-svn: 55533
2008-08-29 07:42:03 +00:00
c139c221dd
addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 encode the opcode.
...
llvm-svn: 55531
2008-08-29 07:40:52 +00:00
9f717afd68
MVN is addrmode1.
...
llvm-svn: 55530
2008-08-29 07:36:24 +00:00
ee98fa9db2
More refactoring.
...
llvm-svn: 55528
2008-08-29 06:41:12 +00:00
960b17a3c2
Swap fp comparison operands and change predicate to allow load folding.
...
llvm-svn: 55521
2008-08-28 23:48:31 +00:00
2d37f19ef2
Refactor ARM instruction format definitions into a separate file. No functionality changes.
...
llvm-svn: 55518
2008-08-28 23:39:26 +00:00
d58f3e36d0
Add a target callback for FastISel.
...
llvm-svn: 55512
2008-08-28 23:21:34 +00:00
95d77f5466
remove tabs, fix > 80 cols
...
llvm-svn: 55511
2008-08-28 23:19:51 +00:00
f304a7aa4d
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
...
llvm-svn: 55504
2008-08-28 21:40:38 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
...
llvm-svn: 55499
2008-08-28 21:04:05 +00:00
26d54b3ef3
Use resize instead of reserve. Reserve doesn't change size().
...
llvm-svn: 55486
2008-08-28 18:32:53 +00:00
a32affb9ba
Implement partial-word binary atomics on ppc.
...
llvm-svn: 55478
2008-08-28 17:53:09 +00:00
97af20f85f
FsFLD0S{S|D} and V_SETALLONES are as cheap as moves.
...
llvm-svn: 55466
2008-08-28 07:52:25 +00:00
41be0d4445
Split the ATOMIC NodeType's to include the size, e.g.
...
ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.
This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad. This is the alternative.
llvm-svn: 55457
2008-08-28 02:44:49 +00:00
76105a4a4f
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
...
SSE2 registers as well as the MMX registers.
llvm-svn: 55436
2008-08-27 21:32:04 +00:00
7f2777e8d2
Reinstate the x86-64 portion of r55190. When doing extloads into
...
64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.
llvm-svn: 55422
2008-08-27 17:33:15 +00:00
abfdf928d8
disallow direct access to SDValue::ResNo, provide a getter instead
...
llvm-svn: 55394
2008-08-26 22:36:50 +00:00
42ccd39689
These assertions should be return false's instead, allowing the client to detect the failure.
...
llvm-svn: 55377
2008-08-26 18:50:40 +00:00
27fb3dcbc7
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
...
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
llvm-svn: 55375
2008-08-26 18:03:31 +00:00
09f8cef571
If an xmm register is referenced explicitly in an inline asm, make sure to
...
assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
2008-08-26 06:19:02 +00:00
4884f87822
This is done.
...
llvm-svn: 55348
2008-08-26 01:13:44 +00:00
d4eb0521e4
Implement 32 & 64 bit versions of PPC atomic
...
binary primitives.
llvm-svn: 55343
2008-08-25 22:34:37 +00:00
2da2e65d7d
80 col. violations.
...
llvm-svn: 55341
2008-08-25 21:58:43 +00:00
f00f1e50b5
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
...
llvm-svn: 55338
2008-08-25 21:27:18 +00:00
765065c982
Remove PPC-specific lowering for atomics; the
...
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
llvm-svn: 55336
2008-08-25 21:09:52 +00:00
166d6cb1fa
It's important for the cmp-and-swap to balance
...
loads and stores but it's even more important for
it to store the right value.:(
llvm-svn: 55319
2008-08-25 18:53:26 +00:00
6cfd3830fb
Nevermind. This broke the bootstrap (?!).
...
llvm-svn: 55318
2008-08-25 18:32:39 +00:00
dd6759aea7
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
...
instructions on having SSE2.
llvm-svn: 55317
2008-08-25 18:20:52 +00:00
e414681352
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
...
llvm-svn: 55300
2008-08-25 04:11:42 +00:00
5b836c5f77
Temporarily reverting r55292. It's causing a bootstraping failure:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
llvm-svn: 55295
2008-08-24 21:45:30 +00:00
8fa17424f7
Move callseq_start above the call address load to allow load to be folded into the call node.
...
llvm-svn: 55292
2008-08-24 19:19:55 +00:00
404cd15fa5
Use additionnal include directory instead of ../ in #include.
...
Suggested by aKor.
llvm-svn: 55282
2008-08-24 12:30:46 +00:00
0c19df4871
Switch the asmprinter (.ll) and all the stuff it requires over to
...
use raw_ostream instead of std::ostream. Among other goodness,
this speeds up llvm-dis of kc++ with a release build from 0.85s
to 0.49s (88% faster).
Other interesting changes:
1) This makes Value::print be non-virtual.
2) AP[S]Int and ConstantRange can no longer print to ostream directly,
use raw_ostream instead.
3) This fixes a bug in raw_os_ostream where it didn't flush itself
when destroyed.
4) This adds a new SDNode::print method, instead of only allowing "dump".
A lot of APIs have both std::ostream and raw_ostream versions, it would
be useful to go through and systematically anihilate the std::ostream
versions.
This passes dejagnu, but there may be minor fallout, plz let me know if
so and I'll fix it.
llvm-svn: 55263
2008-08-23 22:23:09 +00:00
31099519d0
Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
...
Is there way to avoid explicit target check?
llvm-svn: 55238
2008-08-23 15:53:19 +00:00
eb0cee91f6
Move the point at which FastISel taps into the SelectionDAGISel
...
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
llvm-svn: 55219
2008-08-23 02:25:05 +00:00
9f0d0639ca
Make option variables static, so they won't cause nameclash
...
llvm-svn: 55203
2008-08-22 21:27:49 +00:00
fc4f64eed0
Reverting r55190, r55191, and r55192. They broke the build with this error message:
...
{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1
llvm-svn: 55200
2008-08-22 20:51:05 +00:00
736779f088
Anyext tweaks for x86. When extloading a value to i32 or i64, choose
...
instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.
llvm-svn: 55190
2008-08-22 19:19:31 +00:00
ed86f689cb
Implement __sync_synchronize on ppc32. Patch by Gary Benson.
...
llvm-svn: 55186
2008-08-22 17:20:54 +00:00
dec51704ed
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
...
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
llvm-svn: 55163
2008-08-22 03:49:10 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
...
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
2fd7dbaf1d
If part of the mask is "undef", then ignore it as we don't care what goes into it.
...
llvm-svn: 55147
2008-08-21 22:36:36 +00:00
765d3e0013
Fix whitespace. No functionality change.
...
llvm-svn: 55146
2008-08-21 22:35:37 +00:00
9534ea03e8
Fix a number of byval / memcpy / memset related codegen issues.
...
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
llvm-svn: 55139
2008-08-21 21:00:15 +00:00
5c2ac4a5e0
Treat floating point ST1 the same as ST0 when lowering for a call result
...
llvm-svn: 55135
2008-08-21 19:54:16 +00:00
c6337ac069
Add libm-oriented ISD opcodes for rounding operations.
...
llvm-svn: 55130
2008-08-21 17:55:02 +00:00
f16134141d
Allow inline asm nodes with empty bodies inside JIT.
...
This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)
llvm-svn: 55128
2008-08-21 17:33:01 +00:00
d3582c9bda
Simplify SelectRoot's interface, and factor out some common code
...
from all targets.
llvm-svn: 55124
2008-08-21 16:36:34 +00:00
75eeeb399e
Clean up whitespace.
...
llvm-svn: 55117
2008-08-21 08:38:54 +00:00
c1270f8eac
unbreak the CBE on treeadd an many others.
...
llvm-svn: 55112
2008-08-21 05:51:43 +00:00
9371964f47
Use raw_ostream throughout the AsmPrinter.
...
llvm-svn: 55092
2008-08-21 00:14:44 +00:00
814f291664
Move the handling of ANY_EXTEND, SIGN_EXTEND_INREG, and TRUNCATE
...
out of X86ISelDAGToDAG.cpp C++ code and into tablegen code.
Among other things, using tablegen for these things makes them
friendlier to FastISel.
Tablegen can handle the case of i8 subregs on x86-32, but currently
the C++ code for that case uses MVT::Flag in a tricky way, and it
happens to schedule better in some cases. So for now, leave the
C++ code in place to handle the i8 case on x86-32.
llvm-svn: 55078
2008-08-20 21:27:32 +00:00
02c84b8910
Simplify FastISel's constructor argument list, make the FastISel
...
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.
llvm-svn: 55076
2008-08-20 21:05:57 +00:00
3ad7e96f8a
Clean up a dead return missed in r55055.
...
llvm-svn: 55057
2008-08-20 15:54:46 +00:00
8823b0d245
Tablegen generated code already tests the opcode value, so it's not
...
necessary to use dyn_cast in these predicates.
llvm-svn: 55055
2008-08-20 15:24:22 +00:00
c8f9da50ec
Use cast instead of dyn_cast.
...
llvm-svn: 55052
2008-08-20 14:50:24 +00:00
a21bdda961
Fix comment spacing.
...
llvm-svn: 55047
2008-08-20 13:46:21 +00:00
6f765f392c
Add remaining 64-bit atomic patterns for x86-64.
...
llvm-svn: 55029
2008-08-20 00:48:50 +00:00
f00f3055d8
Revert r55018 and apply the correct "fix" for the 64-bit sub_and_fetch atomic.
...
Just expand it like the other X-bit sub_and_fetches.
llvm-svn: 55023
2008-08-20 00:28:16 +00:00
e79740851f
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code
...
was already present, but not hooked up to anything.
llvm-svn: 55018
2008-08-19 23:09:18 +00:00
daef7f43af
Instantiate FastISel for X86.
...
llvm-svn: 55011
2008-08-19 21:45:35 +00:00
4619e93bd3
The X86 target will soon have an implementation of createFastISel.
...
llvm-svn: 55010
2008-08-19 21:32:53 +00:00
5afbf510aa
Add support for 8 and 16 bit forms of __sync
...
builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
llvm-svn: 54999
2008-08-19 18:47:28 +00:00
d7dd8b8aeb
add a note
...
llvm-svn: 54985
2008-08-19 06:22:16 +00:00
f076d5eea8
add a note
...
llvm-svn: 54964
2008-08-19 00:41:02 +00:00
927b5a5ac2
remove empty file
...
llvm-svn: 54950
2008-08-18 21:27:19 +00:00
4ebf3009ed
Unbreak cpp backend: upgrade output due to change in APInt API
...
llvm-svn: 54942
2008-08-18 20:03:45 +00:00
0d19699e52
ARM asm printer can't handle dwarf info yet.
...
llvm-svn: 54913
2008-08-18 08:52:48 +00:00
ab35bfdf18
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman.
...
llvm-svn: 54903
2008-08-17 19:22:34 +00:00
aa8ab4501a
Don't require Registry specializations to define random static variables.
...
llvm-svn: 54902
2008-08-17 19:08:34 +00:00
d930f913e6
Rename some GC classes so that their roll will hopefully be clearer.
...
In particular, Collector was confusing to implementors. Several
thought that this compile-time class was the place to implement
their runtime GC heap. Of course, it doesn't even exist at runtime.
Specifically, the renames are:
Collector -> GCStrategy
CollectorMetadata -> GCFunctionInfo
CollectorModuleMetadata -> GCModuleInfo
CollectorRegistry -> GCRegistry
Function::getCollector -> getGC (setGC, hasGC, clearGC)
Several accessors and nested types have also been renamed to be
consistent. These changes should be obvious.
llvm-svn: 54899
2008-08-17 18:44:35 +00:00
954553c4ce
Make it compile on VC2005:
...
- update VC projects.
- Add an overload to llvm::Stream for <<, since std::hex and std::dec have type std::ios_base& (*)(std::ios_base&) in VC++. (templating the function don't work, due to ambiguities)
- add ../ on several include in X86/AsmPrinter/
llvm-svn: 54898
2008-08-17 18:24:26 +00:00
17d28de8ac
Move ARM to pluggable asmprinter
...
llvm-svn: 54889
2008-08-17 13:55:10 +00:00
19fed1eb3d
Use correct name for PPC codegen library
...
llvm-svn: 54888
2008-08-17 13:54:44 +00:00
28dc9d0ad9
Factor out asmprinter out of ppc
...
llvm-svn: 54887
2008-08-17 13:54:28 +00:00
c5faeb82b5
Move X86 assembler printers into separate directory. This allows JIT-only users not to link it in (use 'x86codegen' llvm-config arg for this)
...
llvm-svn: 54886
2008-08-17 13:53:59 +00:00
17f7165f84
Rework the routines that convert AP[S]Int into a string. Now, instead of
...
returning an std::string by value, it fills in a SmallString/SmallVector
passed in. This significantly reduces string thrashing in some cases.
More specifically, this:
- Adds an operator<< and a print method for APInt that allows you to
directly send them to an ostream.
- Reimplements APInt::toString to be much simpler and more efficient
algorithmically in addition to not thrashing strings quite as much.
This speeds up llvm-dis on kc++ by 7%, and may also slightly speed up the
asmprinter. This also fixes a bug I introduced into the asmwriter in a
previous patch w.r.t. alias printing.
llvm-svn: 54873
2008-08-17 07:19:36 +00:00
16d5d3fba7
PPC/Linux normally uses named section for bss
...
llvm-svn: 54847
2008-08-16 12:59:02 +00:00
c3f3aea666
Use proper strings section name for PPC
...
llvm-svn: 54846
2008-08-16 12:58:46 +00:00
93584cd5a0
Use correct name for TLS address resolution routine on x86-64
...
llvm-svn: 54845
2008-08-16 12:58:29 +00:00
2ae5446b62
Add interface for section override. Use this for Sparc, since it should use named BSS section.
...
llvm-svn: 54844
2008-08-16 12:58:12 +00:00
bd890b1faf
Move SLEB/ULEB size calculation routines from AsmPrinter to TargetAsmInfo. This makes JIT asmprinter-free.
...
llvm-svn: 54843
2008-08-16 12:57:46 +00:00
44b4a9a05d
Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations
...
llvm-svn: 54842
2008-08-16 12:57:07 +00:00
f665aa981a
Build the X86GenFastISel.inc file.
...
llvm-svn: 54806
2008-08-14 23:18:11 +00:00
7c2bf62b14
Also avoid pinsrw and pinsrb with a variable insertelement index.
...
llvm-svn: 54803
2008-08-14 22:53:18 +00:00
4f6bf04616
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
...
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
65d83ccf26
Don't try to use the insertps instruction for vector
...
element inserts with non-constant indices. This fixes
CodeGen/X86/vector-variable-idx.ll on machines that
have SSE4.1.
llvm-svn: 54801
2008-08-14 22:43:26 +00:00
1b351d42bb
Remove more uses of std::set.
...
llvm-svn: 54787
2008-08-14 21:01:00 +00:00
e81ac0b66f
Oops, check in these files too, for the FastISel -> Fast rename.
...
llvm-svn: 54750
2008-08-13 19:55:00 +00:00
92c64ae2d0
Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT node
...
is lowered properly and covers everything LowerSELECT_CC did.
Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This
avoid the ugly instruction by instruction checking in printOperand.
Added a swap instruction present in the allegrex core.
Added two conditional instructions present in the allegrex core : MOVZ and MOVN.
They both allow a more efficient SELECT operation for integers.
Also added SELECT patterns to optimize MOVZ and MOVN usage.
The brcond and setcc patterns were cleaned: redundant and suboptimal patterns
were
removed. The suboptimals were replaced by more efficient ones.
Fixed some instructions that were using immZExt16 instead of immSExt16.
llvm-svn: 54724
2008-08-13 07:13:40 +00:00
40f83ac649
When resolving a stub in x86-64 JIT, use a PC-relative branch
...
rather than the absolute address if the target is within range.
llvm-svn: 54708
2008-08-12 23:20:24 +00:00
30e5dbb407
Make x86-64 JIT changes Darwin-specific.
...
llvm-svn: 54700
2008-08-12 21:02:08 +00:00
643e60e19c
Whitespace cleanup. Test commit.
...
llvm-svn: 54695
2008-08-12 18:34:45 +00:00
d4a5e8f74a
In the absence of a linker to build the GOT, use the 32-bit
...
non_lazy_ptr mechanism on x86-64 Darwin JIT. Fixes a bunch
of last night's failures.
llvm-svn: 54692
2008-08-12 18:23:48 +00:00
dafdbf77b3
Some fixes for x86-64 JIT. Make it use small code
...
model, except for external calls; this makes
addressing modes PC-relative. Incomplete.
The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.
llvm-svn: 54656
2008-08-11 23:46:25 +00:00
f69d13b60a
Implement ISD::TRAP support on PPC
...
llvm-svn: 54644
2008-08-11 17:36:31 +00:00
113b336caa
move some more stuff out of my email into readme.txt
...
llvm-svn: 54603
2008-08-10 01:14:08 +00:00
4afb010309
add a note
...
llvm-svn: 54602
2008-08-10 00:47:21 +00:00
4e2f3ace2c
Add an EXTRACTPSmr pattern to match the pattern that
...
X86ISelLowering creates.
llvm-svn: 54544
2008-08-08 18:30:21 +00:00
bc506bbfdb
Properly print flags on Sparc
...
llvm-svn: 54543
2008-08-08 18:26:10 +00:00
793108b561
Generalize
...
llvm-svn: 54542
2008-08-08 18:25:52 +00:00
f6e3411aec
Use mergeable strings sections on sparc
...
llvm-svn: 54541
2008-08-08 18:25:29 +00:00
ed47329174
Handle visibility printing with all generality. Remove bunch of duplicate code.
...
llvm-svn: 54540
2008-08-08 18:25:07 +00:00
f1f8aa3e50
Use chars, where possible
...
llvm-svn: 54539
2008-08-08 18:24:10 +00:00
c9ad17c3da
Convert PPC/Linux to new section printing stuff
...
llvm-svn: 54538
2008-08-08 18:23:49 +00:00
5b5d8bcd88
Switch PPC/Darwin to new section handling stuff
...
llvm-svn: 54537
2008-08-08 18:23:25 +00:00
7c20ede085
Cleanup
...
llvm-svn: 54536
2008-08-08 18:22:59 +00:00
df8c7faf60
Undo most of r54519.
...
llvm-svn: 54534
2008-08-08 17:56:50 +00:00
655fa0fec4
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
...
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
319548b93c
Fix indentation.
...
llvm-svn: 54518
2008-08-08 06:43:59 +00:00
93da7e6924
Support added for ctlz intrinsic, test case added.
...
llvm-svn: 54516
2008-08-08 06:16:31 +00:00
70e41caf17
Match raw "psp" triple target, as done by the homebrew toolchain.
...
llvm-svn: 54514
2008-08-08 04:49:42 +00:00
02ff450f13
Added Mips support for DYNAMIC_STACKALLOC
...
Fixed bug in adjustMipsStackFrame, which was breaking
while trying to access a dead stack object index. Also added
one more alignment before fixing the callee saved registers
stack offset adjustment.
llvm-svn: 54485
2008-08-07 19:08:11 +00:00
f4f2a0d0e5
Remove dead forward decl
...
llvm-svn: 54461
2008-08-07 09:55:25 +00:00
9dbbd75068
Print section flags ok on platforms, which use '@' as comment string. Fix test.
...
llvm-svn: 54460
2008-08-07 09:55:06 +00:00
1c2de10861
Add assertion for easy debugging of missing stuff
...
llvm-svn: 54459
2008-08-07 09:54:40 +00:00
04083529df
Switch ARM to new section handling stuff
...
llvm-svn: 54458
2008-08-07 09:54:23 +00:00
08faaedc58
Switch Alpha to new section handling stuff
...
llvm-svn: 54457
2008-08-07 09:53:57 +00:00
adb9353da3
Use EmitAlignment consistently
...
llvm-svn: 54456
2008-08-07 09:53:38 +00:00
adcf3f9313
Cleanup
...
llvm-svn: 54455
2008-08-07 09:53:13 +00:00
0e32dffacc
Cleanup
...
llvm-svn: 54454
2008-08-07 09:52:54 +00:00
456e940844
Switch IA64 to new section-handling stuff
...
llvm-svn: 54453
2008-08-07 09:52:35 +00:00
e0157465b7
Cleanup
...
llvm-svn: 54452
2008-08-07 09:52:13 +00:00
8ab2f49536
Provide convenient helpers
...
llvm-svn: 54451
2008-08-07 09:51:54 +00:00
1a11e8a6fe
Switch Sparc to new section handling stuff. Refactor printing of module-level GVs significantly.
...
llvm-svn: 54450
2008-08-07 09:51:25 +00:00
6c7b43cccd
Add hook for constant pool section selection for darwin.
...
llvm-svn: 54449
2008-08-07 09:51:02 +00:00
ef643a4850
Select section for constant pool entries
...
llvm-svn: 54448
2008-08-07 09:50:34 +00:00
527ca7e253
Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
...
LowerSubregs, and fix an x86-64 isel bug that this exposed.
SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.
llvm-svn: 54444
2008-08-07 02:54:50 +00:00
91c2c432c0
Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,
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this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.
llvm-svn: 54418
2008-08-06 18:27:21 +00:00
04f4c833e9
xchg does not modify FLAGS.
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llvm-svn: 54411
2008-08-06 15:52:50 +00:00
4659aad624
Added support for fp callee saved registers.
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Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the
stack the fp callee saved registers are.
Fixed the stack frame layout for Mips, now the callee saved regs
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :
1) FP and RA are also callee saved, and despite they aren't in CSI they
must be saved before the fp callee saved registers.
2) The ABI requires that local varibles are allocated before the callee
saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
other.
llvm-svn: 54403
2008-08-06 06:14:43 +00:00
7823a411d5
Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64.
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llvm-svn: 54376
2008-08-05 22:19:15 +00:00
3da016d137
Trim #includes.
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llvm-svn: 54350
2008-08-05 15:32:23 +00:00
bbeb8f0807
This option doesn't need to be a target option. It can be in SDISel instead.
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llvm-svn: 54336
2008-08-05 00:27:28 +00:00
a102290bdc
- Fix SelectionDAG to generate correct CFGs.
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- Add a basic machine-level dead block eliminator.
These two have to go together, since many other parts of the code generator are unable to handle the unreachable blocks otherwise created.
llvm-svn: 54333
2008-08-04 23:54:43 +00:00
8ef79ebd5f
Add an assert to catch invalid VECTOR_SHUFFLE mask indices.
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llvm-svn: 54329
2008-08-04 23:09:15 +00:00
a01ede2f11
Mips ISelLowering cleanup : Removed old LowerCALL and FORMAL_ARGS helpers, they
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aren't used anyway, they also used to broke compiling when fastcc was specified for a
function, but not anymore.
llvm-svn: 54316
2008-08-04 07:12:52 +00:00
2ca70df58b
Handle i32->f32 bitconvert results.
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llvm-svn: 54315
2008-08-04 06:44:31 +00:00
77e3e86e70
Add atomic sub for other sizes
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llvm-svn: 54314
2008-08-03 20:17:34 +00:00
796e9be3b1
Emit saveri with the correct operand order, patch by Richard Pennington!
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llvm-svn: 54313
2008-08-03 18:16:14 +00:00
3e667cfe21
Fix PR2615
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llvm-svn: 54312
2008-08-03 15:37:43 +00:00
3d4bdcc1a6
Improved asm inline for hi,lo results
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Added hi,lo registers to be used,def implicitly. This provides better handle of
instructions which use hi/lo.
Fixes a small BranchAnalysis bug
llvm-svn: 54274
2008-08-02 19:42:36 +00:00
3397298b65
Apply the same pattern used in 'and' lowering for 'or'
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llvm-svn: 54273
2008-08-02 19:37:33 +00:00
e4798c83d0
Expand fcopysign
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llvm-svn: 54250
2008-07-31 18:50:54 +00:00
23471047be
Handle more SELECT corner cases considering legalize types, probabily wont work with
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the default legalizer.
llvm-svn: 54249
2008-07-31 18:31:28 +00:00
c31eb205c1
Add a flag to disable jump table generation (all
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switches use the binary search algorithm) for
environments that don't support it. PPC64 JIT
is such an environment; turn the flag on for that.
llvm-svn: 54248
2008-07-31 18:13:12 +00:00
2d7ddea240
Added pattern for floating point zero immediate (avoiding a constant pool
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access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.
llvm-svn: 54229
2008-07-30 19:00:31 +00:00
86b06335aa
Reapply r54147 with a constraint to only use the 8-bit
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subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.
Also, change several 16-bit instructions to use
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.
llvm-svn: 54223
2008-07-30 18:09:17 +00:00
a950422221
Fixed bug in global address lowering for functions and in Brcond lowering
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llvm-svn: 54215
2008-07-30 17:06:13 +00:00
57e17f0e14
Removed small section flag for mips, the assembler doesnt support this flag
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llvm-svn: 54214
2008-07-30 17:04:04 +00:00
f714e25f7e
Added new features to represent specific instructions groups
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llvm-svn: 54213
2008-07-30 17:01:06 +00:00
89e2b163fb
Instruction definition cleanup
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llvm-svn: 54212
2008-07-30 16:58:59 +00:00
2a24157364
Changed some methods order.
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llvm-svn: 54169
2008-07-29 19:29:50 +00:00
82f1925708
Fix broken CellSPU lowering, re-instate braces in Legalize
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llvm-svn: 54168
2008-07-29 19:07:27 +00:00
Evan Cheng