010e9b0760
Add RCBarriers to TargetInstrDesc. It's a list of register classes the given instruction can "clobber". For example, on x86 the call instruction can modify all of the XMM and fp stack registers.
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TableGen has been taught to generate the lists from instruction definitions.
llvm-svn: 57722
2008-10-17 21:00:09 +00:00
fc4ad7de66
Move instruction flag inference out of InstrInfoEmitter and into
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CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags.
This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.
llvm-svn: 49123
2008-04-03 00:02:49 +00:00
42c63ef96e
start inferring 'no side effects'.
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llvm-svn: 45822
2008-01-10 05:39:30 +00:00
e457fd1e9b
remove some old hacky code that tried to infer whether a store
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occured in a pattern, but failed miserably. The new code works for
any instruction that has a store in its pattern, including all the
x86 mem op mem instructions.
The only target-independent code that uses this is branch folding,
so this won't change anything in practice.
llvm-svn: 45648
2008-01-06 02:16:26 +00:00
27a4c1515a
rearrange some code to allow inferring instr info from the pattern of the instr, but don't do so yet.
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llvm-svn: 45647
2008-01-06 01:53:37 +00:00
85467a17ae
final cleanups.
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llvm-svn: 45644
2008-01-06 01:21:51 +00:00
626b89daa4
further simplifications and cleanup
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llvm-svn: 45643
2008-01-06 01:20:13 +00:00
827efa451f
simplify some code
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llvm-svn: 45642
2008-01-06 01:12:44 +00:00
e59a3c79e5
split enum emission out from InstrInfoEmitter into it's own tblgen backend.
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llvm-svn: 45640
2008-01-06 00:49:05 +00:00
8adcd9f32e
remove attributions from utils.
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llvm-svn: 45419
2007-12-29 20:37:13 +00:00
33f5a51020
simplify the way operand flags and constraints are handled, making it easier
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to extend.
llvm-svn: 31481
2006-11-06 23:49:51 +00:00
7d6f3db3e2
Unbreak VC++ build.
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llvm-svn: 31464
2006-11-05 19:31:28 +00:00
ac79c7c4c0
Add operand constraints to TargetInstrInfo.
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llvm-svn: 31333
2006-11-01 00:27:05 +00:00
0433df136f
Emit itinerary class in instruction info.
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llvm-svn: 24122
2005-10-31 17:16:46 +00:00
742606ad30
Switch more code over to using getValueAsListOfDefs. Look at all the -'s. :)
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llvm-svn: 24074
2005-10-28 22:59:53 +00:00
d02bd5bb05
Emit real operand info for instructions. This currently works but is bad
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in one way: the generated tables require dynamic initialization for the
register classes. This will be fixed in a future patch.
llvm-svn: 22919
2005-08-19 18:46:26 +00:00
99df668f48
When emitting implicit use/def lists, only emit each unique list once. Though
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LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data. This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.
This should speed up the register allocator as well by reducing the dcache
footprint for this static data.
llvm-svn: 22879
2005-08-18 21:36:47 +00:00
650ba8eb56
Remove trailing whitespace
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llvm-svn: 21428
2005-04-22 00:00:37 +00:00
7dfc2d29ac
Convert 'struct' to 'class' in various places to adhere to the coding standards
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and work better with VC++. Patch contributed by Morten Ofstad!
llvm-svn: 17281
2004-10-27 16:14:51 +00:00
c860ecafe1
Add, and start using, the CodeGenInstruction class. This class represents
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an instance of the Instruction tablegen class.
llvm-svn: 15385
2004-08-01 05:04:00 +00:00
960707c335
Put all LLVM code into the llvm namespace, as per bug 109.
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llvm-svn: 9903
2003-11-11 22:41:34 +00:00
d3032037f1
Added LLVM copyright header.
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llvm-svn: 9305
2003-10-20 20:20:30 +00:00
f5bd1b7a8e
Move support/tools/* back into utils
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llvm-svn: 8875
2003-10-05 19:27:59 +00:00
Evan Cheng