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239 Commits

Author SHA1 Message Date
Evan Cheng f02bb9af8b * Commit the fix (by Chris) for a tblgen type inferencing bug. 
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.

llvm-svn: 24587
 2005-12-04 08:18:16 +00:00
Nate Begeman 006bb04f3a Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Nate Begeman faad542d24 Nuke CodeGenInstruction's ValueType member, it is no longer used. 
llvm-svn: 24556
 2005-12-01 00:12:04 +00:00
Nate Begeman 4d0251ad55 Add the new vector types to tablegen 
llvm-svn: 24514
 2005-11-29 06:19:38 +00:00
Chris Lattner f2807be3da Initialize this variable on all paths, fixing a crasher in windows. Thanks 
to JeffC for pointing this out.

llvm-svn: 24426
 2005-11-19 07:48:33 +00:00
Chris Lattner 6bc0304c91 Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!

llvm-svn: 24424
 2005-11-19 07:05:57 +00:00
Chris Lattner 7ad0bed89f Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately 
reflect what it is.
Convert some more code over to use it.

llvm-svn: 24072
 2005-10-28 22:49:02 +00:00
Chris Lattner 90c5b9c83c Do not let getLegalValueTypes return a list with duplicates in it 
llvm-svn: 23723
 2005-10-14 03:54:49 +00:00
Chris Lattner 3ced3f8b82 force all instruction operands to be named. 
llvm-svn: 23358
 2005-09-14 21:13:50 +00:00
Chris Lattner f02994d782 Check that operands have unique names. REJECT instructions with broken operand 
lists: only don't parse them if they are entirely missing (sparcv9).

llvm-svn: 23355
 2005-09-14 21:05:02 +00:00
Chris Lattner ae939eb6bb Add a new Record::getValueAsCode method to mirror the other getValueAs* 
methods.  Use it to simplify some code.

llvm-svn: 23336
 2005-09-13 21:44:28 +00:00
Chris Lattner cee994b464 Compute the value types that are natively supported by a target. 
llvm-svn: 23282
 2005-09-08 21:43:21 +00:00
Chris Lattner c6a0338c04 spell this right 
llvm-svn: 23099
 2005-08-26 20:55:40 +00:00
Chris Lattner 63dc7f569a spell this variable right 
llvm-svn: 23095
 2005-08-26 20:42:52 +00:00
Chris Lattner 3d9fbefbf7 Expose a new flag to TargetInstrInfo 
llvm-svn: 23094
 2005-08-26 20:40:46 +00:00
Chris Lattner 73ec2cb0f5 Split register class "Methods" into MethodProtos and MethodBodies 
llvm-svn: 22928
 2005-08-19 19:12:51 +00:00
Chris Lattner 418d8cfcfe Read the namespace field from register classes 
llvm-svn: 22918
 2005-08-19 18:45:20 +00:00
Chris Lattner 0899614152 Fix a problem jeffc noticed 
llvm-svn: 22903
 2005-08-19 06:16:04 +00:00
Chris Lattner 17727bad02 Figure out how many operands each instruction has, keep track of whether 
or not it's variable.

llvm-svn: 22885
 2005-08-18 23:38:41 +00:00
Misha Brukman 650ba8eb56 Remove trailing whitespace 
llvm-svn: 21428
 2005-04-22 00:00:37 +00:00
Chris Lattner 945e8655dd Refactor code for numbering instructions into CodeGenTarget. 
llvm-svn: 19758
 2005-01-22 18:58:51 +00:00
Chris Lattner 733c82bfbf Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. 
llvm-svn: 19243
 2005-01-02 02:29:04 +00:00
Misha Brukman 243ded5e1a * Add option to read isLittleEndianEncoding for InstrInfo classes 
* Doxygen-ify some function comments

llvm-svn: 16974
 2004-10-14 05:50:43 +00:00
Chris Lattner 91c538f2a1 Add initial support for variants. This just parses the new format, no 
functionality is added

llvm-svn: 16636
 2004-10-03 19:34:31 +00:00
Nate Begeman 996ddbc98e Add support for the isLoad and isStore flags, needed by the instruction scheduler 
llvm-svn: 16554
 2004-09-28 21:01:45 +00:00
Chris Lattner 9b0dfa3c0d Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG 
llvm-svn: 16553
 2004-09-28 18:38:01 +00:00
Chris Lattner 8eab62ee0d Alignment is now in bits. 
llvm-svn: 15976
 2004-08-21 20:15:25 +00:00
Chris Lattner beadefde19 Make alignment be in bits, just like size is 
llvm-svn: 15969
 2004-08-21 20:00:36 +00:00
Chris Lattner d3244d9cec Support "Methods" in register classes in CodgeGenRegisterClass 
llvm-svn: 15965
 2004-08-21 19:21:21 +00:00
Chris Lattner 2a86fab933 Start parsing register classes into a more structured form 
llvm-svn: 15961
 2004-08-21 04:05:00 +00:00
Chris Lattner e34ae99942 Read in declared reg sizes 
llvm-svn: 15960
 2004-08-21 02:24:57 +00:00
Chris Lattner 8af61ddb96 Use CodeGenRegister class to make reading in of register information more 
systematic.

llvm-svn: 15805
 2004-08-16 01:10:21 +00:00
Chris Lattner 6ffa501d9f Make the AsmWriter a first-class tblgen object. Allow targets to specify 
name of the generated asmwriter class, and the name of the format string.

llvm-svn: 15747
 2004-08-14 22:50:53 +00:00
Chris Lattner 3bc477a237 Start parsing more information from the Operand information 
llvm-svn: 15644
 2004-08-11 02:22:39 +00:00
Chris Lattner 101f3fea82 Remove special case hacks 
llvm-svn: 15643
 2004-08-11 01:53:58 +00:00
Chris Lattner 5572682faa Parse the operand list of the instruction. We currently support register and immediate operands. 
llvm-svn: 15390
 2004-08-01 07:42:39 +00:00
Chris Lattner 1c4ae85035 Initial cut at an asm writer emitter. So far, this only handles emission of 
instructions, and only instructions that take no operands at that!

llvm-svn: 15386
 2004-08-01 05:59:33 +00:00
Chris Lattner c860ecafe1 Add, and start using, the CodeGenInstruction class. This class represents 
an instance of the Instruction tablegen class.

llvm-svn: 15385
 2004-08-01 05:04:00 +00:00
Chris Lattner fce9603387 Rename CodeGenWrappers.(cpp|h) -> CodeGenTarget.(cpp|h) 
llvm-svn: 15382
 2004-08-01 04:04:35 +00:00