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370 Commits

Author SHA1 Message Date
Jim Grosbach fc5451832a Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
llvm-svn: 140095
 2011-09-19 23:31:02 +00:00
Jim Grosbach 05541f45f3 Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Jim Grosbach 8221319707 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
llvm-svn: 140047
 2011-09-19 20:29:33 +00:00
Jim Grosbach 40700e0992 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

llvm-svn: 140035
 2011-09-19 18:42:21 +00:00
Jim Grosbach d0c435c23c Thumb2 assembly parsing and encoding for SUB(immediate). 
llvm-svn: 139966
 2011-09-16 22:58:42 +00:00
Jim Grosbach 9c0b86a76d Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

llvm-svn: 139949
 2011-09-16 21:55:56 +00:00
Jim Grosbach 099c9767c3 Thumb2 assembly parsing and encoding for STMIA. 
llvm-svn: 139938
 2011-09-16 20:50:13 +00:00
Jim Grosbach d73c6458de Thumb2 assembly parsing and encoding for SMMULL. 
llvm-svn: 139921
 2011-09-16 18:05:48 +00:00
Jim Grosbach 5e6d5cd7da Kill some dead code. 
llvm-svn: 139904
 2011-09-16 16:45:40 +00:00
Jim Grosbach 6c45b75154 Tidy up a bit. 
llvm-svn: 139903
 2011-09-16 16:39:25 +00:00
Jim Grosbach f9799d2c2d Thumb2 assembly parsing and encoding for SMLAL. 
llvm-svn: 139902
 2011-09-16 16:38:00 +00:00
Owen Anderson d7791b961c Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
llvm-svn: 139747
 2011-09-14 22:46:14 +00:00
Jim Grosbach 9c8b9932d6 Thumb2 assembly parsing and encoding for MUL. 
llvm-svn: 139735
 2011-09-14 21:00:40 +00:00
Jim Grosbach 0ecd395095 Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

llvm-svn: 139721
 2011-09-14 20:03:46 +00:00
Jim Grosbach 18b8b17579 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

llvm-svn: 139714
 2011-09-14 19:12:11 +00:00
Jim Grosbach 3ac26b138b ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573

llvm-svn: 139707
 2011-09-14 18:08:35 +00:00
Jim Grosbach 75461af000 Remove unnecessary scope resolution operator. 
llvm-svn: 139656
 2011-09-13 22:56:44 +00:00
Jim Grosbach e3a6a82f16 There's only 16 regs legal in a register list. 
llvm-svn: 139637
 2011-09-13 20:35:57 +00:00
Owen Anderson 44ae2da4ec Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
llvm-svn: 139610
 2011-09-13 17:59:19 +00:00
Jim Grosbach 3337e396c8 Tidy up a bit. 
llvm-svn: 139559
 2011-09-12 23:36:42 +00:00
Jim Grosbach b908b7af31 Thumb2 parsing and encoding for MOV(immediate). 
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.

llvm-svn: 139440
 2011-09-10 00:15:36 +00:00
Owen Anderson 29cfe6c368 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Jim Grosbach 62c33955e2 Thumb2 assembly parsing and encoding for MLA and MLS. 
llvm-svn: 139399
 2011-09-09 20:24:45 +00:00
Jim Grosbach a05627ebaf Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Jim Grosbach 7db8d697cf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Jim Grosbach c086f689f8 Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback. 
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.

llvm-svn: 139270
 2011-09-08 00:39:19 +00:00
Jim Grosbach 2392c53e73 Thumb2 assembly parsing and encoding for LDRBT. 
llvm-svn: 139267
 2011-09-07 23:39:14 +00:00
Jim Grosbach e0ebc1c396 Thumb2 assembly parsing and encoding for LDR(register). 
llvm-svn: 139264
 2011-09-07 23:10:15 +00:00
Jim Grosbach 5bfa8bab06 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254
 2011-09-07 20:58:57 +00:00
Jim Grosbach a31f223af8 Thumb2 parsing and encoding for LDMIA. 
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.

llvm-svn: 139242
 2011-09-07 18:05:34 +00:00
Jim Grosbach 39c6e1d66d Better diagnostic location information for mnemonic suffices. 
llvm-svn: 139232
 2011-09-07 16:06:04 +00:00
Jim Grosbach 803898f119 Thumb2 parsing and encoding for CLREX. 
llvm-svn: 139172
 2011-09-06 20:27:04 +00:00
Jim Grosbach f471ac3c72 ARM .code directive should always go to the streamer. 
Even if there's no mode switch performed, the .code directive should still
be sent to the output streamer. Otherwise, for example, an output asm stream
is not equivalent to the input stream which generated it (a dependency on
the input target triple arm vs. thumb is introduced which was not originally
there).

llvm-svn: 139155
 2011-09-06 18:46:23 +00:00
Jim Grosbach a0d34d3b5e Thumb2 parsing and encoding of B instruction. 
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.

llvm-svn: 139049
 2011-09-02 23:22:08 +00:00
Jim Grosbach f6d5d60f99 ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code. 
llvm-svn: 138952
 2011-09-01 18:22:13 +00:00
Owen Anderson 35d240f9e8 t2Bcc is allowed to have a predicate without a preceding IT instruction. 
llvm-svn: 138946
 2011-09-01 17:47:45 +00:00
Jim Grosbach 1d3c137839 Thumb2 assembly parsing and encoding for ADD(immediate). 
llvm-svn: 138922
 2011-09-01 00:28:52 +00:00
Jim Grosbach 99bc84662f Thumb2 t2Bcc should encode as t2B when condition is 'always'. 
llvm-svn: 138898
 2011-08-31 21:17:31 +00:00
Jim Grosbach cfa9421e16 Remove FIXME. Thumb2 MOV instruction will use separate custom tricks. 
When we want encoding T3 (the wide encoding), we can explicitly check for
that and twiddle the CanAcceptCarrySet accordingly. For now, just correctly
handle encodings T1 and T2 when in Thumb2 mode.

llvm-svn: 138879
 2011-08-31 18:39:39 +00:00
Jim Grosbach c61fc8f301 tBcc is OK to be predicated in Thumb2 outside of IT blocks (obviously). 
llvm-svn: 138873
 2011-08-31 18:29:05 +00:00
Jim Grosbach 6d606fbe14 Tweak Thumb1 ADD encoding selection a bit. 
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.

llvm-svn: 138862
 2011-08-31 17:07:33 +00:00
Jim Grosbach ed16ec4248 Thumb2 parsing and encoding for IT blocks. 
llvm-svn: 138773
 2011-08-29 22:24:09 +00:00
Owen Anderson 967674d26c Improve handling of #-0 offsets for many more pre-indexed addressing modes. 
llvm-svn: 138754
 2011-08-29 19:36:44 +00:00
Owen Anderson f02d98d7c0 Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it. 
llvm-svn: 138739
 2011-08-29 17:17:09 +00:00
Jim Grosbach b9d4e37776 ARM assembly parsing tweak for pldw. 
llvm-svn: 138669
 2011-08-26 22:21:51 +00:00
Jim Grosbach 3d1eac85c3 Thumb2 assembler parsing and encoding of IT instruction. 
This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.

llvm-svn: 138665
 2011-08-26 21:43:41 +00:00
Owen Anderson 16d33f36d5 invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. 
llvm-svn: 138653
 2011-08-26 20:43:14 +00:00
Jim Grosbach 1c171b121a Explicitly disallow predication in Thumb1 assembly. 
llvm-svn: 138562
 2011-08-25 17:23:55 +00:00
Jim Grosbach 838ed3af46 Thumb .n mnemonic qualifiers can be ignored for now. 
We'll need to pay attention to them when we start getting more serious about
the details of parsing thumb2 assembly.

llvm-svn: 138500
 2011-08-24 22:19:48 +00:00
Jim Grosbach 4b701af908 Thumb parsing and encoding for SUB (SP minu immediate). 
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.

llvm-svn: 138494
 2011-08-24 21:42:27 +00:00
Jim Grosbach 0a0b3071df Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.

llvm-svn: 138488
 2011-08-24 21:22:15 +00:00
Jim Grosbach 6ccd79f4d5 Add missing explicit writeback operand to tSTMIA_UPD. 
rdar://10014745

llvm-svn: 138457
 2011-08-24 18:19:42 +00:00
Evan Cheng 2bb4035707 Move TargetRegistry and TargetSelect from Target to Support where they belong. 
These are strictly utilities for registering targets and components.

llvm-svn: 138450
 2011-08-24 18:08:43 +00:00
Evan Cheng 4d6c9d711d Some refactoring so TargetRegistry.h no longer has to include any files 
from MC.

llvm-svn: 138367
 2011-08-23 20:15:21 +00:00
Jim Grosbach d80d169a04 Thumb parsing and encoding for STM. 
llvm-svn: 138345
 2011-08-23 18:15:37 +00:00
Jim Grosbach 169b2be611 Factor low reg checking into a helper function. 
llvm-svn: 138344
 2011-08-23 18:13:04 +00:00
Jim Grosbach 3636be3c8f Thumb parsing and encoding for SBC. 
llvm-svn: 138311
 2011-08-22 23:55:58 +00:00
Jim Grosbach c3c32d9e09 Thumb parsing and encoding for RSB. 
llvm-svn: 138308
 2011-08-22 23:47:13 +00:00
Jim Grosbach 38c59fcb08 Improve error checking for tPUSH and tPOP register lists. 
llvm-svn: 138295
 2011-08-22 23:17:34 +00:00
Jim Grosbach 139acd21e6 Thumb assemmbly parsing diagnostic improvements for LDM. 
llvm-svn: 138287
 2011-08-22 23:01:07 +00:00
Jim Grosbach 5c932b24be Tighten up ARM reglist validation a bit. 
llvm-svn: 138258
 2011-08-22 18:50:36 +00:00
Jim Grosbach 2597722e07 Thumb parsing and encoding support for NOP. 
The irony is not lost that this is not a completely trivial patchset.

llvm-svn: 138143
 2011-08-19 23:24:36 +00:00
Jim Grosbach 37aa348195 Thumb assembly parsing and encoding for NEG. 
llvm-svn: 138131
 2011-08-19 22:51:03 +00:00
Jim Grosbach 459422d750 Be more lenient on tied operand matching for MUL. 
llvm-svn: 138124
 2011-08-19 22:30:46 +00:00
Jim Grosbach 8e048495c8 Thumb assembly parsing and encoding for MUL. 
llvm-svn: 138108
 2011-08-19 22:07:46 +00:00
Jim Grosbach f86cd37bef Thumb assembly parsing and encoding for MOV. 
llvm-svn: 138076
 2011-08-19 20:46:54 +00:00
Jim Grosbach 5503c3a4e8 Thumb assembly parsing and encoding for LSL(immediate). 
llvm-svn: 138063
 2011-08-19 19:29:25 +00:00
Jim Grosbach 26d3587bd8 Thumb assembly parsing and encoding for LDRH. 
llvm-svn: 138060
 2011-08-19 18:55:51 +00:00
Jim Grosbach a32c753ebf Thumb assembly parsing and encoding for LDRB. 
llvm-svn: 138059
 2011-08-19 18:49:59 +00:00
Jim Grosbach 23983d6bd9 Thumb assembly parsing and encoding for LDR(immediate) form T2. 
llvm-svn: 138050
 2011-08-19 18:13:48 +00:00
Jim Grosbach 7473329725 Use helper function to check for low registers. 
llvm-svn: 138048
 2011-08-19 17:57:22 +00:00
Jim Grosbach 3fe94e3ef8 Thumb assembly parsing and encoding for LDR(immediate) form T1. 
llvm-svn: 138047
 2011-08-19 17:55:24 +00:00
Jim Grosbach 90103ccc05 Thumb assembly parsing and encoding for LDM instruction. 
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.

llvm-svn: 137986
 2011-08-18 21:50:53 +00:00
Jim Grosbach 6ddb568ab8 Add missing 'break'. 
llvm-svn: 137941
 2011-08-18 16:08:39 +00:00
Jim Grosbach cbd4ab104b Thumb assembly parsing and encoding for B. 
llvm-svn: 137891
 2011-08-17 22:57:40 +00:00
Jim Grosbach d3e8e29124 Thumb assembly parsing and encoding for ASR. 
llvm-svn: 137889
 2011-08-17 22:49:09 +00:00
Jim Grosbach 46dd413991 ARM clean up the imm_sr operand class representation. 
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.

llvm-svn: 137879
 2011-08-17 21:51:27 +00:00
Jim Grosbach e9ab47a72a Thumb ADD(immediate) parsing support. 
llvm-svn: 137788
 2011-08-16 23:57:34 +00:00
Jim Grosbach b7fa2c0a53 Thumb parsing diagnostics for low-reg requirements on ADD and MOV. 
llvm-svn: 137779
 2011-08-16 22:20:01 +00:00
Jim Grosbach 64610e52e7 Add missing exit for 'case'. 
llvm-svn: 137774
 2011-08-16 21:42:31 +00:00
Jim Grosbach 58ffdccab1 Thumb assembly parsing and encoding for ADD(register) instruction. 
llvm-svn: 137759
 2011-08-16 21:34:08 +00:00
Jim Grosbach 7283da9bb2 Move some logic into a helper function and expand the commentary. 
llvm-svn: 137756
 2011-08-16 21:12:37 +00:00
Jim Grosbach 3e941aee69 ARM thumb assembly parsing for arithmetic flag setting instructions. 
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.

llvm-svn: 137746
 2011-08-16 20:45:50 +00:00
Jim Grosbach 120a96a721 MCTargetAsmParser target match predicate support. 
Allow a target assembly parser to do context sensitive constraint checking
on a potential instruction match. This will be used, for example, to handle
Thumb2 IT block parsing.

llvm-svn: 137675
 2011-08-15 23:03:29 +00:00
Jim Grosbach 8cffa28af8 ARM vector compare to zero instruction assembly parsing support. 
llvm-svn: 137389
 2011-08-11 23:51:13 +00:00
Jim Grosbach a2b8b60646 ARM load shifted register pre-index fix shift value asm parser encoding. 
llvm-svn: 137367
 2011-08-11 22:05:09 +00:00
Jim Grosbach d886f8cd8d ARM STRH assembly parsing and encoding. 
llvm-svn: 137353
 2011-08-11 21:17:22 +00:00
Jim Grosbach eb09f49a7f ARM STRD assembly parsing and encoding. 
llvm-svn: 137342
 2011-08-11 20:28:23 +00:00
Jim Grosbach d564bf3181 ARM STR(immediate) assembly parsing and encoding. 
llvm-svn: 137331
 2011-08-11 19:22:40 +00:00
Jim Grosbach 27ad83d8a9 ARM push of a single register encodes as pre-indexed STR. 
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.

llvm-svn: 137318
 2011-08-11 18:07:11 +00:00
Jim Grosbach 8ba76c6d5c ARM pop of a single register encodes as post-indexed LDR. 
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.

llvm-svn: 137316
 2011-08-11 17:35:48 +00:00
Jim Grosbach cd4dd255c0 ARM LDRH(immediate) assembly parsing and encoding support. 
llvm-svn: 137260
 2011-08-10 22:42:16 +00:00
Jim Grosbach 1d9d5e93d1 ARM LDRD(register) assembly parsing and encoding. 
Add support for literal encoding of #-0 along the way.

llvm-svn: 137254
 2011-08-10 21:56:18 +00:00
Jim Grosbach f7164b2cfd Fix typo. Not quite sure how that slipped in there. 
llvm-svn: 137245
 2011-08-10 20:49:18 +00:00
Jim Grosbach 5b96b80644 ARM LDRD(immediate) assembly parsing and encoding support. 
llvm-svn: 137244
 2011-08-10 20:29:19 +00:00
Jim Grosbach 95466ce63b ARM load/store label parsing. 
Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.

llvm-svn: 137064
 2011-08-08 20:59:31 +00:00
Jim Grosbach 3d0b3a3a50 ARM load instruction shifted register index operands. 
Parsing and encoding for shifted index operands for load instructions.

llvm-svn: 136986
 2011-08-05 22:03:36 +00:00
Jim Grosbach c320c85261 ARM indexed load assembly parsing and encoding. 
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.

llvm-svn: 136982
 2011-08-05 21:28:30 +00:00
Jim Grosbach a70fbfd577 ARM simplify the postidx_reg operand encoding. 
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.

llvm-svn: 136969
 2011-08-05 16:11:38 +00:00
Jim Grosbach cd17c12078 ARM assembly parsing and encoding for LDR instructions. 
Enhance support for LDR instruction assembly parsing for post-indexed
addressing with immediate values. Add tests.

llvm-svn: 136940
 2011-08-04 23:01:30 +00:00