llvm-project

Commit Graph

Author	SHA1	Message	Date
David Green	9f15fcc271	[ARM] Replace arm_neon_vqadds with sadd_sat This replaces the A32 NEON vqadds, vqaddu, vqsubs and vqsubu intrinsics with the target independent sadd_sat, uadd_sat, ssub_sat and usub_sat. This helps generate vqadds from standard IR nodes, which might be produced from the vectoriser. The old variants are removed in the process. Differential Revision: https://reviews.llvm.org/D69350	2019-11-27 13:32:29 +00:00
Roger Ferrer Ibanez	5a2a14db0b	[TargetLowering] Simplify expansion of S{ADD,SUB}O ISD::SADDO uses the suggested sequence described in the section §2.4 of the RISCV Spec v2.2. ISD::SSUBO uses the dual approach but checking for (non-zero) positive. Differential Revision: https://reviews.llvm.org/D47927 llvm-svn: 373187	2019-09-30 07:58:50 +00:00
Nikita Popov	e44691bf9f	Move thumbv7k test from AArch64 to ARM As pointed out by charukcs on rL361166, this test uses an ARM triple. llvm-svn: 361220	2019-05-21 06:24:36 +00:00

Author

SHA1

Message

Date

David Green

9f15fcc271

[ARM] Replace arm_neon_vqadds with sadd_sat

This replaces the A32 NEON vqadds, vqaddu, vqsubs and vqsubu intrinsics
with the target independent sadd_sat, uadd_sat, ssub_sat and usub_sat.
This helps generate vqadds from standard IR nodes, which might be
produced from the vectoriser. The old variants are removed in the
process.

Differential Revision: https://reviews.llvm.org/D69350

2019-11-27 13:32:29 +00:00

Roger Ferrer Ibanez

5a2a14db0b

[TargetLowering] Simplify expansion of S{ADD,SUB}O

ISD::SADDO uses the suggested sequence described in the section §2.4 of
the RISCV Spec v2.2. ISD::SSUBO uses the dual approach but checking for
(non-zero) positive.

Differential Revision: https://reviews.llvm.org/D47927

llvm-svn: 373187

2019-09-30 07:58:50 +00:00

Nikita Popov

e44691bf9f

Move thumbv7k test from AArch64 to ARM

As pointed out by charukcs on rL361166, this test uses an ARM triple.

llvm-svn: 361220

2019-05-21 06:24:36 +00:00

3 Commits