Commit Graph

7 Commits

Author SHA1 Message Date
Richard Osborne 3c31e21837 Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission.
This change adds XCoreMCInstLower to do the lowering to MCInst and
XCoreInstPrinter to print the MCInsts.

llvm-svn: 170288
2012-12-16 16:20:48 +00:00
Jia Liu b22310fda6 Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Jakob Stoklund Olesen b93331f3be Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

llvm-svn: 100384
2010-04-05 03:10:20 +00:00
Richard Osborne 692f6e7f9d Remove xs1b predicate since it is no longer needed to differentiate betweem
xs1a and xs1b.

llvm-svn: 83383
2009-10-06 16:17:57 +00:00
Richard Osborne d7b887410d Remove xs1a subtarget. xs1a is a preproduction device used in
early development boards which is no longer supported in the
XMOS toolchain.

llvm-svn: 83381
2009-10-06 16:01:09 +00:00
Evan Cheng 977e7be9d4 Move target independent td files from lib/Target/ to include/llvm/Target so they can be distributed along with the header files.
llvm-svn: 59953
2008-11-24 07:34:46 +00:00
Richard Osborne ca08e0645a Add XCore backend.
llvm-svn: 58838
2008-11-07 10:59:00 +00:00