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21 Commits

Author SHA1 Message Date
Richard Osborne 038d24f90c [XCore] Add missing l2rus instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173634
 2013-01-27 22:28:30 +00:00
Richard Osborne f2ecd40929 [XCore] Add missing l2r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173629
 2013-01-27 21:26:02 +00:00
Richard Osborne 7fe8f63544 [XCore] Add missing 1r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173624
 2013-01-27 20:46:21 +00:00
Richard Osborne 8f56317287 [XCore] Add missing 0r instructions. 
These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 173623
 2013-01-27 20:42:57 +00:00
Richard Osborne 6b86eec819 Add instruction encodings / disassembly support for l4r instructions. 
llvm-svn: 173501
 2013-01-25 21:55:32 +00:00
Richard Osborne a19fa86a70 Add instruction encodings / disassembly support for l5r instructions. 
llvm-svn: 173479
 2013-01-25 20:20:07 +00:00
Richard Osborne 54e311821f Add instruction encodings / disassembly support for l6r instructions. 
llvm-svn: 173288
 2013-01-23 20:08:11 +00:00
Richard Osborne 1a06479f46 Add instruction encodings / disassembly support for u10 / lu10 instructions. 
llvm-svn: 173204
 2013-01-22 22:55:04 +00:00
Richard Osborne 9d3ec06ef8 Add instruction encodings / disassembly support for u6 / lu6 instructions. 
llvm-svn: 173086
 2013-01-21 20:44:17 +00:00
Richard Osborne 6e58c6d86d Add instruction encoding / disassembly support for ru6 / lru6 instructions. 
llvm-svn: 173085
 2013-01-21 20:42:16 +00:00
Richard Osborne 4e69724869 Add instruction encodings / disassembly support for l2rus instructions. 
llvm-svn: 172987
 2013-01-20 18:51:15 +00:00
Richard Osborne 9fbf57b26c Add instruction encodings / disassembly support for l3r instructions. 
llvm-svn: 172986
 2013-01-20 18:37:49 +00:00
Richard Osborne f063fcee7a Add instruction encodings / disassembler support for 2rus instructions. 
llvm-svn: 172985
 2013-01-20 17:22:43 +00:00
Richard Osborne 3fb7395233 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

llvm-svn: 172984
 2013-01-20 17:18:47 +00:00
Richard Osborne 459e35c261 Add instruction encodings / disassembly support for l2r instructions. 
llvm-svn: 170345
 2012-12-17 16:28:02 +00:00
Richard Osborne 51bf1b269a Add instruction encodings for PEEK and ENDIN. 
Previously these were marked with the wrong format.

llvm-svn: 170334
 2012-12-17 14:23:54 +00:00
Richard Osborne 041071c558 Add instruction encodings / disassembly support for rus instructions. 
llvm-svn: 170330
 2012-12-17 13:50:04 +00:00
Richard Osborne e405e58639 Add instruction encodings for ZEXT and SEXT. 
Previously these were marked with the wrong format.

llvm-svn: 170327
 2012-12-17 13:20:37 +00:00
Richard Osborne 3a0d5cc314 Add instruction encodings / disassembly support for 2r instructions. 
llvm-svn: 170323
 2012-12-17 12:29:31 +00:00
Richard Osborne 016967e4ff Add instruction encodings / disassembly support for 0r instructions. 
llvm-svn: 170322
 2012-12-17 12:26:29 +00:00
Richard Osborne c5287b8889 Add tests for disassembly of 1r XCore instructions. 
llvm-svn: 170295
 2012-12-16 18:06:30 +00:00