2 Commits

Author	SHA1	Message	Date
Heejin Ahn	b3724b7169	[WebAssembly] Support for a ternary atomic RMW instruction ... Summary: This adds support for a ternary atomic RMW instruction: cmpxchg. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49195 llvm-svn: 338617	2018-08-01 19:40:28 +00:00
Heejin Ahn	8daef0751d	[WebAssembly] Add tests for weaker memory consistency orderings ... Summary: Currently all wasm atomic memory access instructions are sequentially consistent, so even if LLVM IR specifies weaker orderings than that, we should upgrade them to sequential ordering and treat them in the same way. Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D49194 llvm-svn: 337854	2018-07-24 21:06:44 +00:00