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18396 Commits

Author SHA1 Message Date
Eli Friedman ea8c66fea5 Get rid of an incorrect optimization for shuffles with PALIGNR and simplify isPALIGNRMask. 
Addresses PR10466, although the crash from that PR only triggers in cases where DAGCombine misses optimizing a shuffle.

llvm-svn: 135980
 2011-07-25 21:36:45 +00:00
Evan Cheng 9eec764c15 Fix more MC layering violations. 
llvm-svn: 135979
 2011-07-25 21:32:49 +00:00
Evan Cheng 21b42e2498 More MC layering violations. 
llvm-svn: 135978
 2011-07-25 21:29:26 +00:00
Rafael Espindola e96fd5a4fe Add LLVMAddTargetLibraryInfo to the C API. 
llvm-svn: 135975
 2011-07-25 21:20:54 +00:00
Evan Cheng 61faa55b74 Separate MCInstPrinter registration from AsmPrinter registration. 
llvm-svn: 135974
 2011-07-25 21:20:24 +00:00
Jim Grosbach 3ddf6aa503 Simply ARM so_reg MIOperandInfo definitions. 
The shift immediate encoding, printing, etc. is handled directly by the
enclosing operand definition, so it should be a vanilla immediate, not a
nested complex operand (shift_imm).

llvm-svn: 135968
 2011-07-25 21:04:58 +00:00
Evan Cheng f60768a14e Fix last bits of MC layer issues. llvm-mc doesn't need to initialize TargetMachine's anymore. 
llvm-svn: 135963
 2011-07-25 20:53:02 +00:00
Jim Grosbach ac798e1533 ARM asm operand renaming. Make things a bit more explicit. 
llvm-svn: 135959
 2011-07-25 20:49:51 +00:00
Jim Grosbach eeaab22166 More simple cleanup of ARM asm operand definitions. 
llvm-svn: 135958
 2011-07-25 20:38:18 +00:00
Evan Cheng f5bf19530b Code clean up. 
llvm-svn: 135954
 2011-07-25 20:18:48 +00:00
Evan Cheng d2e165d48b Refactor MBlaze target to separate MC routines from Target routines. 
llvm-svn: 135953
 2011-07-25 20:18:18 +00:00
Bill Wendling 43ab71a9a8 Update the comment. This feature is available only on Darwin at the moment. Though it's not Darwin-specific. 
llvm-svn: 135951
 2011-07-25 20:15:15 +00:00
Jim Grosbach 2d6ef44d39 Make assembly parser method names more consistent. 
llvm-svn: 135950
 2011-07-25 20:14:50 +00:00
Oscar Fuentes 47d4aaf8ad Unbreak the build. 
llvm-svn: 135949
 2011-07-25 20:13:36 +00:00
Jim Grosbach 46d575acc6 Tidy up formatting. 
Remove some inititalizers that are the same as the default, move defs next to
their (singular) uses and generally simplify some formatting of asm operand
definitions.

llvm-svn: 135946
 2011-07-25 20:06:30 +00:00
Jim Grosbach 5ed9fe8037 Tidy up a bit. 
llvm-svn: 135945
 2011-07-25 20:00:32 +00:00
Evan Cheng 20b31548e6 Missed a file. 
llvm-svn: 135943
 2011-07-25 19:55:33 +00:00
Evan Cheng 61d4a20f0f Refactor PPC target to separate MC routines from Target routines. 
llvm-svn: 135942
 2011-07-25 19:53:23 +00:00
Evan Cheng b25310095f More refactoring. 
llvm-svn: 135939
 2011-07-25 19:33:48 +00:00
Evan Cheng 7e763d86ba Refactor X86 target to separate MC code from Target code. 
llvm-svn: 135930
 2011-07-25 18:43:53 +00:00
Bill Wendling 2dc0005b3c Changed disabled code into a flag. 
llvm-svn: 135924
 2011-07-25 18:04:49 +00:00
Bill Wendling 1d10909cb7 Remove dead variable. 
llvm-svn: 135923
 2011-07-25 18:01:27 +00:00
Bill Wendling b97270d58a After we've modified the prolog to save volatile registers, generate the compact 
unwind encoding for that function. This simply crawls through the prolog looking
for machine instrs marked as "frame setup". It can calculate from these what the
compact unwind should look like.

This is currently disabled because of needed linker support. But initial tests
look good.

llvm-svn: 135922
 2011-07-25 18:00:28 +00:00
Roman Divacky aaba17e89b Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5. 
llvm-svn: 135866
 2011-07-24 08:22:56 +00:00
NAKAMURA Takumi 287bc6bdf6 ARMMCTargetDesc.h: Fixup to add DataTypes.h, or uint32_t would be unavailable. 
llvm-svn: 135837
 2011-07-23 01:16:22 +00:00
Evan Cheng f2596bc62a Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where they belong. 
llvm-svn: 135833
 2011-07-23 00:45:41 +00:00
Evan Cheng 6376593ed1 createXXXMCCodeGenInfo should be static. 
llvm-svn: 135826
 2011-07-23 00:01:04 +00:00
Evan Cheng ad5f485957 Sink ARM mc routines into MCTargetDesc. 
llvm-svn: 135825
 2011-07-23 00:00:19 +00:00
Jim Grosbach 801e0a3fde ARM SSAT instruction 5-bit immediate handling. 
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.

llvm-svn: 135823
 2011-07-22 23:16:18 +00:00
Jim Grosbach e7e1e163db ARM assembly parsing and encoding updates. 
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.

llvm-svn: 135817
 2011-07-22 22:06:05 +00:00
Evan Cheng 8c886a40d2 Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo, 
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.

llvm-svn: 135812
 2011-07-22 21:58:54 +00:00
Bruno Cardoso Lopes a89039998d Fix PR10422 by adding the necessary AVX UCOMISD memory versions to 
load folding logic

llvm-svn: 135801
 2011-07-22 20:53:20 +00:00
Jim Grosbach 8dfcc0bb92 ARM assembly parsing and encoding of SMLAL instruction. 
Fix parsing of carry-setting variant SMLALS and add tests.

llvm-svn: 135797
 2011-07-22 20:18:21 +00:00
Jim Grosbach d7c8c35301 ARM encoding and assembly parsing of SMLAD{X} instructions. 
Fix encoding of destination register. Add tests.

llvm-svn: 135796
 2011-07-22 20:11:20 +00:00
Bruno Cardoso Lopes d23a324132 Add v8f32->v8i32 bitcast. Fixes PR10440 
llvm-svn: 135794
 2011-07-22 19:51:02 +00:00
Rafael Espindola 77242dd537 Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64 
too. Patch by Jeff Muizelaar.

llvm-svn: 135789
 2011-07-22 18:56:05 +00:00
Dan Gohman c535278cf1 Fix x86's XALUO lowering to return its replacement values instead 
of doing the RAUW calls for the overflow value itself. This makes
it more consistent with how the rest of LegalizeDAG works.

llvm-svn: 135788
 2011-07-22 18:45:15 +00:00
Owen Anderson 3fa7ca84d9 Fix test failures caused by my so_reg refactoring. 
llvm-svn: 135785
 2011-07-22 18:30:30 +00:00
Jim Grosbach d1f8bde10f ARM assembly parsing and encoding for SMC instruction. 
llvm-svn: 135782
 2011-07-22 18:13:31 +00:00
Jim Grosbach bc9d841878 Clean up a few more comments. 
These instruction definitions are for the assembler, too, not just the
disassembler.

llvm-svn: 135781
 2011-07-22 18:06:01 +00:00
Jim Grosbach 163eb27c1a Tidy up. 
llvm-svn: 135779
 2011-07-22 18:04:10 +00:00
Jim Grosbach 39f9388a9d Thumb assembly support for SETEND instruction. 
llvm-svn: 135778
 2011-07-22 17:52:23 +00:00
Jim Grosbach 9afae0d01b Tidy up. 
llvm-svn: 135777
 2011-07-22 17:46:13 +00:00
Jim Grosbach 0a547701a4 ARM assembly parsing and encoding for SETEND instruction. 
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.

llvm-svn: 135776
 2011-07-22 17:44:50 +00:00
Jim Grosbach 41d084f807 Tidy up. 
llvm-svn: 135771
 2011-07-22 16:59:04 +00:00
Chandler Carruth 43025a0869 Move TargetRegistry.cpp from lib/Support to lib/Target where it belongs. 
The header file was already properly located. The previous need for it
in Support had to do with the version string printing which was fixed in
r135757.

Also update build dependencies where libraries that needed the
functionality of the Target library (in the form of the TargetRegistry)
were picking it up via Support. This is pretty pervasive, essentially
every TargetInfo library (ARMInfo, etc) uses TargetRegistry, making it
depend on Target. All of these were previously just sneaking by.

llvm-svn: 135760
 2011-07-22 08:16:53 +00:00
Benjamin Kramer 959b7e9df7 GCC complains about the angle of this line. 
Remove the escaped newline.

llvm-svn: 135739
 2011-07-22 01:02:57 +00:00
Bruno Cardoso Lopes 1872173841 Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn't 
the way to go. Doing this here will prevent several node matches later,
and would have to force looking all the way through several
VINSERTF128/VEXTRACTF128 chains to optimize simple things.

llvm-svn: 135730
 2011-07-22 00:15:10 +00:00
Bruno Cardoso Lopes 612e56174b -Inspected a AVX code block added by someone in early Feb. This was never used 
and was actually very wrong, fix it and make it simpler. Also remove the
ConcatVectors function, which is unused now.

- Fix a introduction of useless nodes in r126664 and r126264. The
VUNPCKL* should never be introduced cause we don't want duplicate
nodes for 128 AVX and non-AVX modes, the actual instruction
difference only exists during isel, but not for target specific DAG
nodes. We only introduce V* target nodes when there is no 128-bit
version already there.

- Fix a fragile test and make it more useful.

llvm-svn: 135729
 2011-07-22 00:15:07 +00:00
Bruno Cardoso Lopes 91eff5140f Add a DAGCombine for transforming 128->256 casts into a simple 
vxorps + vinsertf128 pair of instructions

llvm-svn: 135727
 2011-07-22 00:15:00 +00:00