a20cde31e7
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
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llvm-svn: 135636
2011-07-20 23:34:39 +00:00
229907cd11
land David Blaikie's patch to de-constify Type, with a few tweaks.
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llvm-svn: 135375
2011-07-18 04:54:35 +00:00
194c3dc01f
Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.
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llvm-svn: 134030
2011-06-28 21:14:33 +00:00
6cc775f905
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
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sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
llvm-svn: 134021
2011-06-28 19:10:37 +00:00
0713a9d8fc
Add a parameter to CCState so that it can access the MachineFunction.
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No functional change.
Part of PR6965
llvm-svn: 132763
2011-06-08 23:55:35 +00:00
86585798af
Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.
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rdar://9431157
llvm-svn: 132522
2011-06-03 01:13:19 +00:00
6528a54946
Fix ARM fast isel to correctly flag memory operands to stores. This fixes
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-verify-machineinstrs failures on several tests.
llvm-svn: 132268
2011-05-28 20:34:49 +00:00
fe84bd659c
Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
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llvm-svn: 132194
2011-05-27 18:02:04 +00:00
c70355195c
Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
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The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).
rdar://9437928 .
llvm-svn: 132099
2011-05-25 23:49:02 +00:00
5bbb75655b
Prepare ARMFastISel::SelectSIToFP for getRegForValue returning registers for i8 and i16 values.
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llvm-svn: 132073
2011-05-25 19:09:45 +00:00
4e983166bc
Kill some dead code.
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llvm-svn: 131431
2011-05-16 22:24:07 +00:00
39b56b4b9f
Apparently the check for direct calls is unnecessary.
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llvm-svn: 130716
2011-05-02 20:16:33 +00:00
328bad02fa
Switch to ImmLeaf (which can be used by FastISel) for a few more common ARM/Thumb2 patterns.
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llvm-svn: 130552
2011-04-29 22:48:03 +00:00
7708746c33
Add FastEmitInst_ii for the arm fast isel generator. It doesn't use it, but
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if it ever did it needs the def machinery.
llvm-svn: 130549
2011-04-29 22:07:50 +00:00
26b8ac4b8c
Some cleanup and optimize fallthrough more.
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llvm-svn: 130546
2011-04-29 21:56:31 +00:00
86caced370
Re-committing r130454, which does not in fact break anything.
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Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
rdar://problem/9338332 .
llvm-svn: 130539
2011-04-29 21:22:56 +00:00
8d46b47787
Add trunc->branch support, this won't help with clang's i8->i1 truncations
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for bools, but is a start.
llvm-svn: 130534
2011-04-29 20:02:39 +00:00
9ade5e2495
Update comments and checks to match reality.
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llvm-svn: 130464
2011-04-29 00:07:20 +00:00
501d2e2c14
Whitespace.
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llvm-svn: 130463
2011-04-29 00:03:10 +00:00
517728b1ae
Revert r130454; apparently this doesn't actually work.
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llvm-svn: 130462
2011-04-28 23:55:14 +00:00
e4ecd42926
Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register.
...
rdar://problem/9338332 .
llvm-svn: 130454
2011-04-28 23:03:25 +00:00
4f012fd0a1
Be more layout aware here and swap the successor and branch condition
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if it means we get a fallthrough.
llvm-svn: 130404
2011-04-28 16:52:09 +00:00
ebddfe60a0
Correct result when a branch condition is live across a block
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boundary. <rdar://problem/8933028>
llvm-svn: 129634
2011-04-16 03:31:26 +00:00
7c14a558fe
Don't include Operator.h from InstrTypes.h.
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llvm-svn: 129271
2011-04-11 09:35:34 +00:00
b968f4defe
Just use BL all the time. It's safer that way.
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Fixes rdar://9184526
llvm-svn: 128869
2011-04-05 00:39:26 +00:00
53dd03d537
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
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can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
a5a779ef45
Migrate the fix in r128041 to ARM's fastisel support as well.
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Fixes rdar://9169640
llvm-svn: 128100
2011-03-22 19:39:17 +00:00
174d872702
Sometimes isPredicable lies to us and tells us we don't need the operands.
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Go ahead and add them on when we might want to use them and let
later passes remove them.
Fixes rdar://9118569
llvm-svn: 127518
2011-03-12 01:09:29 +00:00
919772fd5d
Only use blx for external function calls on thumb, these could be fixed
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up by the dynamic linker, but it's better to use the correct instruction
to begin with.
Fixes rdar://9011034
llvm-svn: 126176
2011-02-22 01:37:10 +00:00
331cc5218d
Use the incoming VT not the VT of where we're trying to store to determine
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if we can store a value. Also, the exclusion is or, not and.
Fixes rdar://8920247.
llvm-svn: 124357
2011-01-27 05:44:56 +00:00
249fcd4499
Remove unused variables found by gcc-4.6's -Wunused-but-set-variable.
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llvm-svn: 123707
2011-01-18 00:51:23 +00:00
dfce83c8f5
Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
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movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0
It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.
llvm-svn: 123619
2011-01-17 08:03:18 +00:00
1b3f5b9f74
fix some -Wself-assign warnings.
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llvm-svn: 122893
2011-01-05 18:41:05 +00:00
c874f6c9ff
Arm and thumb call instructions are also in different orders.
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Fixes rdar://8782223
llvm-svn: 122313
2010-12-21 03:50:43 +00:00
347f4c32e8
Don't handle -arm-long-calls in fast isel for now.
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llvm-svn: 121919
2010-12-15 23:47:29 +00:00
119ff7ff04
Refactor load/store handling again. Simplify and make some room for
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reg+reg handling.
llvm-svn: 120526
2010-12-01 01:40:24 +00:00
78b4efb472
Noticed this on inspection, fix and update some comments.
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llvm-svn: 120447
2010-11-30 19:14:07 +00:00
43b0c6d94f
Update fastisel for the changes in r120272.
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llvm-svn: 120324
2010-11-29 21:56:23 +00:00
527da1b6e2
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
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llvm-svn: 119990
2010-11-23 03:31:01 +00:00
0a3c28bd6b
Rewrite address handling to use a structure with all the possible address
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mode variables. Handle frame indexes in load/store and allocas again.
llvm-svn: 119912
2010-11-20 22:38:27 +00:00
d0aec3bf64
STRH only needs the additional operand, not t2STRH. Also invert conditional
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to match the one from the load emitter above.
llvm-svn: 119911
2010-11-20 22:01:38 +00:00
35e2d7f610
Don't need to save piecemeal now.
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llvm-svn: 119862
2010-11-19 22:39:56 +00:00
cee83d6e6b
Update comment.
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llvm-svn: 119861
2010-11-19 22:37:58 +00:00
558b61e2d4
Update comment.
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llvm-svn: 119859
2010-11-19 22:36:41 +00:00
fef5f315af
Refactor address mode handling into a single struct (ala x86), this
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should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
d7a3550a5e
Remove hard tabs.
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llvm-svn: 119810
2010-11-19 18:01:37 +00:00
964943780b
Recommit this change and remove the failing part of the test - it didn't
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pass in the first place and was masked by earlier failures not warning
and aborting the block.
llvm-svn: 119184
2010-11-15 21:11:06 +00:00
1293c6a23a
Temporarily revert this.
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llvm-svn: 118946
2010-11-12 23:50:48 +00:00
49a66f7d71
Make this happen for ARM like x86. Don't entirely bail out when
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an address is in a different block, get it into a register and go
from there.
llvm-svn: 118936
2010-11-12 22:52:32 +00:00
22d0492f34
Fix up a few more spots of addrmode2 (or not) changes that were
...
missed. Update some comments accordingly.
Fixes rdar://8652289
llvm-svn: 118888
2010-11-12 09:48:30 +00:00
Evan Cheng