fecdad6237
Reimplement BuildResultOperands to be in terms of the result instruction's
...
operand list instead of the operand list redundantly declared on the alias
or instruction.
With this change, we finally remove the ins/outs list on the alias. Before:
def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
def : InstAlias<"movsx $src, $dst",
(MOVSX16rr8W GR16:$dst, GR8:$src)>;
This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.
llvm-svn: 118329
2010-11-06 07:14:44 +00:00
46c2acbcb4
Allow targets to specify the MachO CPUType/CPUSubtype information.
...
llvm-svn: 118288
2010-11-05 18:48:58 +00:00
98512315f7
When passing a huge parameter using the byval mechanism, a long
...
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead. PR7170.
llvm-svn: 118260
2010-11-04 21:16:46 +00:00
71049f78ed
In the calling convention logic, ValVT is always a legal type,
...
and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
1462777017
Simplify uses of MVT and EVT. An MVT can be compared directly
...
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
f5dda01f33
Inside the calling convention logic LocVT is always a simple
...
value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
60d555c178
rearrange a bit.
...
llvm-svn: 117967
2010-11-01 23:07:52 +00:00
865dd96f22
use our fancy new MnemonicAlias mechanism to remove a bunch of hacks
...
from X86AsmParser.cpp
llvm-svn: 117952
2010-11-01 21:06:34 +00:00
1acd6b1edc
"mov[zs]x (mem), GR16" are not ambiguous: the mem
...
must be 8 bits. Support this memory form.
llvm-svn: 117902
2010-11-01 05:41:10 +00:00
dd3b09c234
Implement enough of the missing instalias support to get
...
aliases installed and working. They now work when the
matched pattern and the result instruction have exactly
the same operand list.
This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.
Note that we do not accept instructions like:
movzx 0(%rsp), %rsi
GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand. It could be 8/16/32 bits.
llvm-svn: 117901
2010-11-01 05:34:34 +00:00
178f4bb62d
make the asm matcher emitter reject instructions that have comments
...
in their asmstring. Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.
llvm-svn: 117897
2010-11-01 04:44:29 +00:00
941c19b7ba
reject instructions that contain a \n in their asmstring. Mark
...
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.
llvm-svn: 117884
2010-11-01 00:46:16 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
...
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
9492c17baf
two changes: make the asmmatcher generator ignore ARM pseudos properly,
...
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
llvm-svn: 117861
2010-10-31 19:15:18 +00:00
eb8c0fc2eb
sketch out the planned instruction alias mechanism, add some comments about
...
how the push/pop mnemonic aliases are wrong.
llvm-svn: 117857
2010-10-31 18:43:46 +00:00
fb0a48ef96
Factorize the duplicated logic for choosing the right argument
...
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.
llvm-svn: 117856
2010-10-31 13:21:44 +00:00
fa7e6f2417
Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86,
...
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.
llvm-svn: 117855
2010-10-31 13:02:38 +00:00
aac142cc06
Resolve a terrible hack in tblgen: instead of hardcoding
...
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.
llvm-svn: 117831
2010-10-30 19:38:20 +00:00
2cb092dc55
Implement (and document!) support for MnemonicAlias's to have Requires
...
directives, allowing things like this:
def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;
Move the rest of the X86 MnemonicAliases over to the .td file.
llvm-svn: 117830
2010-10-30 19:23:13 +00:00
57bfc66d60
really zap alias.
...
llvm-svn: 117824
2010-10-30 18:23:25 +00:00
462bc666d2
move fcompi alias to .td file and zap some useless code.
...
llvm-svn: 117823
2010-10-30 18:22:53 +00:00
daae9eea8a
move rep aliases to td file
...
llvm-svn: 117822
2010-10-30 18:17:33 +00:00
fa40aee871
move sal aliases to .td file.
...
llvm-svn: 117821
2010-10-30 18:14:54 +00:00
4d9f157203
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding
...
for shl. Caught by inspection.
llvm-svn: 117820
2010-10-30 18:13:10 +00:00
069132311a
move a bunch more aliases from .cpp -> .td file.
...
llvm-svn: 117819
2010-10-30 18:07:17 +00:00
b4a1674421
move cmov aliases to .td file.
...
llvm-svn: 117818
2010-10-30 17:56:50 +00:00
f04cbe6291
move setcc and jcc aliases from .cpp to .td
...
llvm-svn: 117817
2010-10-30 17:51:45 +00:00
72c0b59e81
move some code.
...
llvm-svn: 117816
2010-10-30 17:38:55 +00:00
ba7b4fea97
implement (and document!) the first kind of MC assembler alias, which
...
just remaps one mnemonic to another. Convert a few of the X86 aliases
from .cpp to .td code.
llvm-svn: 117815
2010-10-30 17:36:36 +00:00
4cf25f5ba9
Clean up comments.
...
llvm-svn: 117785
2010-10-30 13:48:28 +00:00
de30afc3d9
stay out of the reserved namespace
...
llvm-svn: 117773
2010-10-30 04:57:14 +00:00
e8360b7182
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
...
llvm-svn: 117667
2010-10-29 17:29:13 +00:00
9c3f6bf2bf
Fix pastos in handling of AVX cvttsd2si, PR8491.
...
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!
llvm-svn: 117514
2010-10-28 00:35:54 +00:00
5e7cb5fc27
Added the x86 instruction ud2b (2nd official undefined instruction).
...
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
7db918f1e9
x86-Win32: Switch ftol2 calling convention from stdcall to C.
...
llvm-svn: 117474
2010-10-27 18:52:38 +00:00
9ad2166899
Yet another tweak to X86 instructions to add ud2a as an alias to ud2
...
(still to add ud2b).
llvm-svn: 117435
2010-10-27 03:01:02 +00:00
20b021c970
Another tweak to X86 instructions to add the missing flex instruction (without
...
the wait prefix).
llvm-svn: 117434
2010-10-27 02:53:04 +00:00
a1917c7555
Tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler
allows for these instructions. Done differently than in r117031 that
caused a valgrind error which was later reverted.
llvm-svn: 117433
2010-10-27 02:32:19 +00:00
ba985d9dd5
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
...
will accept versions that the darwin assembler allows. Forms ending in "pi" and
forms without all the operands.
llvm-svn: 117427
2010-10-27 00:59:28 +00:00
e660f4d072
Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
...
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet). No functional change except
for dump output.
llvm-svn: 117413
2010-10-26 23:11:10 +00:00
d94f3b4ae9
handle X86::EH_RETURN64 and X86::EH_RETURN.
...
llvm-svn: 117378
2010-10-26 18:09:55 +00:00
e8ae98817a
Implement some relaxations for arithmetic instructions. The limitation
...
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.
llvm-svn: 117364
2010-10-26 14:09:12 +00:00
ec57ac1c3c
An stdcall function calling a non-stdcall function
...
cannot use tailcall. PR 8461.
llvm-svn: 117322
2010-10-25 22:17:05 +00:00
800fd3533c
Add X86::reloc_global_offset_table and use it to have a single place where
...
we check for _GLOBAL_OFFSET_TABLE_.
llvm-svn: 117241
2010-10-24 17:35:42 +00:00
de0a4fbf3b
Make the disassembler tables const so they end up in read-only memory.
...
llvm-svn: 117206
2010-10-23 09:10:44 +00:00
aa19ee17c0
X86: Emit _fltused instead of __fltused on Windows x64.
...
llvm-svn: 117205
2010-10-23 09:06:59 +00:00
9873c9039e
Remove a define which is never referenced.
...
llvm-svn: 117202
2010-10-23 08:25:16 +00:00
88c54b82c1
Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
...
until other LLVM projects using these are cleaned up.
llvm-svn: 117200
2010-10-23 08:10:43 +00:00
1851090515
Making the e_machine configurable by the target backend in ELFObjectWriter.
...
llvm-svn: 117099
2010-10-22 15:52:49 +00:00
edd006c1c3
Reverting r117031 to cleanup valgrind errors.
...
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.
llvm-svn: 117087
2010-10-22 03:58:29 +00:00
9f6c622f88
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
llvm-svn: 117084
2010-10-22 01:24:11 +00:00
0138a05557
More tweaks to X86 instructions to allow the 'w' suffix in places it makes
...
sense, when the instruction takes the 16-bit ax register or m16 memory
location. These changes to llvm-mc matches what the darwin assembler allows
for these instructions. Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).
llvm-svn: 117031
2010-10-21 17:16:46 +00:00
ee4eb2bad1
Remove some variables that are never really used
...
(gcc-4.6 warns about these).
llvm-svn: 117021
2010-10-21 16:03:28 +00:00
1f0d37e892
Add parentheses to pacify gcc, which warns otherwise.
...
llvm-svn: 117020
2010-10-21 16:02:12 +00:00
f509c6ca27
X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424.
...
llvm-svn: 116984
2010-10-21 01:41:01 +00:00
83ce5f181f
CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args.
...
This should be the minimum set of functions that could possibly need it.
llvm-svn: 116978
2010-10-21 00:08:21 +00:00
9cafc872ab
Fix Whitespace.
...
llvm-svn: 116972
2010-10-20 23:40:27 +00:00
320a553319
Remove Synthesizable from the Type system; as MMX vector
...
types are no longer Legal on X86, we don't need it.
No functional change. 8499854.
llvm-svn: 116947
2010-10-20 21:32:10 +00:00
89f6613e76
Handle _GLOBAL_OFFSET_TABLE_ correctly.
...
llvm-svn: 116932
2010-10-20 16:46:08 +00:00
63c7608c34
Re-enable register pressure aware machine licm with fixes. Hoist() may have
...
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.
llvm-svn: 116845
2010-10-19 18:58:51 +00:00
418204e523
Revert r116781 "- Add a hook for target to determine whether an instruction def
...
is", which breaks some nightly tests.
llvm-svn: 116816
2010-10-19 17:14:24 +00:00
3e64de9504
X86: Add MS-CRT libcalls.
...
llvm-svn: 116801
2010-10-19 07:32:52 +00:00
8b382e7e10
Fix Whitespace.
...
llvm-svn: 116800
2010-10-19 07:32:42 +00:00
8249dfe6ce
- Add a hook for target to determine whether an instruction def is
...
"long latency" enough to hoist even if it may increase spilling. Reloading
a value from spill slot is often cheaper than performing an expensive
computation in the loop. For X86, that means machine LICM will hoist
SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
instructions.
- Enable register pressure aware machine LICM by default.
llvm-svn: 116781
2010-10-19 00:55:07 +00:00
49843c0162
Added a few tweaks to the Intel Descriptor-table support instructions to allow
...
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes. This is again for use just with assembly source for llvm-mc .
llvm-svn: 116773
2010-10-19 00:01:44 +00:00
e3dc9e2ea1
Produce ELF::R_386_GOTPC relocations.
...
llvm-svn: 116728
2010-10-18 18:36:12 +00:00
b9783dd9bc
Added a handful of x86-32 instructions that were missing so that llvm-mc would
...
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
llvm-svn: 116716
2010-10-18 17:04:36 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
5e683250ee
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
...
if any floating point arguments are passed to an external function.
llvm-svn: 116665
2010-10-16 08:25:41 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
d565b44a98
Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.
...
llvm-svn: 116368
2010-10-12 23:19:28 +00:00
604e142844
Combine these together - should probably have some text associated
...
that says what why what we just asserted is wrong.
llvm-svn: 116333
2010-10-12 19:44:17 +00:00
eb7b91d417
Mark variable 'NoImplicitFloatOps' used only in an assert as used.
...
llvm-svn: 116323
2010-10-12 18:18:03 +00:00
395a898b2b
Initial va_arg support for x86-64. Patch by David Meyer!
...
llvm-svn: 116319
2010-10-12 18:00:49 +00:00
aec745326a
Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.
...
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.
The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.
llvm-svn: 116314
2010-10-12 17:15:00 +00:00
e01c9001c9
Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand
...
llvm-svn: 116214
2010-10-11 19:02:04 +00:00
8dedb62019
X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents.
...
llvm-svn: 116188
2010-10-11 05:29:15 +00:00
00765e5be0
X86: MinGW should always use libgcc on Windows.
...
llvm-svn: 116177
2010-10-10 23:11:06 +00:00
7a573a5e1f
X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin).
...
llvm-svn: 116174
2010-10-10 22:04:34 +00:00
bee1f7f5ba
Fix Whitespace.
...
llvm-svn: 116173
2010-10-10 22:04:20 +00:00
530ce85b3e
Fix Whitespace.
...
llvm-svn: 116149
2010-10-09 11:00:50 +00:00
c951cfe6a0
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
8eeb5013cd
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
d57f9ecd4a
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
cf97db2402
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
a07b5c291d
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
35e6ce479c
fix a subtle bug I introduced in my refactoring, where we stopped preferring
...
the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
llvm-svn: 116053
2010-10-08 05:12:14 +00:00
dd77477690
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
626656a562
reapply the patch reverted in r116033:
...
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
llvm-svn: 116039
2010-10-08 03:54:52 +00:00
8f21f9c1fb
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
...
'add'", which seems to have broken just about everything.
llvm-svn: 116033
2010-10-08 02:07:32 +00:00
5b2a411c77
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
...
on r116007, which I am about to revert.
llvm-svn: 116032
2010-10-08 02:07:29 +00:00
efdf08b5b8
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
134f415bf8
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
e2245542ce
Use the new TB_NOT_REVERSABLE flag instead of special
...
casing FsMOVAPDrr/FsMOVAPSrr.
llvm-svn: 116016
2010-10-08 00:03:02 +00:00
0921bfdf36
simplify some map operations.
...
llvm-svn: 116014
2010-10-07 23:57:02 +00:00
4fb38d3cd3
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
...
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
llvm-svn: 116007
2010-10-07 23:36:18 +00:00
1c090c00bc
Reduce casting in various tables by defining the table
...
with the right types.
llvm-svn: 116001
2010-10-07 23:08:41 +00:00
70a7b54f97
simplify code: don't build up vector only to assert it is empty.
...
llvm-svn: 115997
2010-10-07 22:26:19 +00:00
f5c60d8156
convert test to use the existing classes that the multipatterns
...
use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
llvm-svn: 115982
2010-10-07 21:31:03 +00:00
ae8d67d3bb
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
5c31bf0619
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
a8c0bbb869
reduce redundancy between pattern copies.
...
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
9fece2bea2
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
...
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
752b60bc01
convert adc/sbb to a multipattern. Because the adde/sube nodes
...
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
llvm-svn: 115964
2010-10-07 20:01:55 +00:00
c6a6e9ba7c
Fix obvious mistake pointed out by Michael Spencer.
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llvm-svn: 115952
2010-10-07 18:47:10 +00:00
67677515ac
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
...
allowing us to convert ADD over. deletes 160 lines of .td file.
llvm-svn: 115897
2010-10-07 01:37:01 +00:00
4fc52f6fa0
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
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Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
llvm-svn: 115896
2010-10-07 01:26:27 +00:00
26d6a0449a
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
b71a77d7b8
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
894d2e6146
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
e17d7212f1
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
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llvm-svn: 115880
2010-10-07 00:12:45 +00:00
b19bae4e3e
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
356f16c142
add the pattern operator to match to X86TypeInfo, use this to
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convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
b2dd88db6b
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
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This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
6e85be2ecf
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
94eff91dc0
add a class for _REV nodes.
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llvm-svn: 115748
2010-10-06 05:35:22 +00:00
a46073b56b
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
b6da2be7e8
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
7bbd809b6c
with tblgen suitably extended, we can now get the load node from typeinfo.
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llvm-svn: 115744
2010-10-06 04:58:43 +00:00
1fc81e90f7
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
eadaeaab93
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
9402633637
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
61ea00b494
allow !strconcat to take more than two operands to eliminate
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!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
97b1368ae3
associate the instruction suffix letter with the integer gpr
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register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
7359194b63
introduce a new BinOpRR class, and convert 4 and instructions to use it.
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llvm-svn: 115715
2010-10-05 23:32:05 +00:00
cff5b0ea36
Move cmov pseudo instructions to InstrCompiler,
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convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
1a1c600110
Use #NAME# to have the CMOV multiclass define things with the same names as before
...
(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
7538ed80a9
enhance tblgen to support anonymous defm's, use this to
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simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
fa25dd9548
convert cmov mr patterns to use a multipattern. Death to redundancy
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and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
0067ee02f9
switch CMOVBE to the multipattern:
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21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
907d86db22
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
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not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
c3a767e9b0
add a multiclass for cmov's, but don't start using it yet.
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llvm-svn: 115692
2010-10-05 22:01:02 +00:00
aa02c1c91d
use a multipattern to define setcc instructions:
...
X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
8f4f1d1136
move SETB pseudos into the same place in InstrCompiler.td
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llvm-svn: 115686
2010-10-05 21:18:04 +00:00
13111b08fb
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
ab85ef9e55
distribute the rest of the contents of X86Instr64bit.td out to
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the right places. X86Instr64bit.td now dies, long live x86-64!
llvm-svn: 115669
2010-10-05 20:49:15 +00:00
27c763d342
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
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llvm-svn: 115663
2010-10-05 20:35:37 +00:00
c2f5e5764f
continue moving 64-bit stuff into X86InstrArithmetic.td
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llvm-svn: 115660
2010-10-05 20:23:31 +00:00
7552d15d19
move 64-bit add and adc to InstrArithmetic.
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llvm-svn: 115632
2010-10-05 16:59:08 +00:00
182e87caaf
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
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llvm-svn: 115631
2010-10-05 16:52:25 +00:00
39c70f4833
split the 32-bit integer arithmetic instructions out to their own file.
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llvm-svn: 115627
2010-10-05 16:39:12 +00:00
1818dd510e
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
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llvm-svn: 115608
2010-10-05 07:13:35 +00:00
1b3aa8678e
move 32-bit shift and rotates out to their own file.
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llvm-svn: 115607
2010-10-05 07:00:12 +00:00
89497a990e
add new file
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llvm-svn: 115606
2010-10-05 06:52:35 +00:00
a68466c202
move sign and zero extensions out to their own file.
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llvm-svn: 115605
2010-10-05 06:52:26 +00:00
84571a1581
move some instructions from Instr64Bit -> InstrInfo.
...
bswap32 doesn't read eflags.
llvm-svn: 115604
2010-10-05 06:47:35 +00:00
da8c94ef44
move CMOV_FR32 and friends to InstrCompiler, since they are
...
pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
llvm-svn: 115603
2010-10-05 06:41:40 +00:00
44a5a2b569
move various pattern matching support goop out of X86Instr64Bit, to live
...
with the 32-bit stuff.
llvm-svn: 115602
2010-10-05 06:37:31 +00:00
fa9b058eef
split conditional moves and setcc's out to their own file.
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llvm-svn: 115601
2010-10-05 06:33:16 +00:00
f9594ba4e7
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
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llvm-svn: 115600
2010-10-05 06:27:48 +00:00
c184a57e98
move the atomic pseudo instructions out to X86InstrCompiler.td
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llvm-svn: 115599
2010-10-05 06:22:35 +00:00
c793f8bca6
move more pseudo instructions out to X86InstrCompiler.td
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llvm-svn: 115598
2010-10-05 06:10:16 +00:00
52d3935dfe
move VMX instructions out to their own file.
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llvm-svn: 115597
2010-10-05 06:06:53 +00:00
ae33f5d93b
continue moving stuff out to X86InstrSystem.td. Move
...
control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
llvm-svn: 115596
2010-10-05 06:04:14 +00:00
dec85b8c64
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
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llvm-svn: 115591
2010-10-05 05:32:15 +00:00
402e54822b
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
d77a443631
va_args support for Win64.
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Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
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Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
bb48e26732
Add 3DNowA instructions.
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llvm-svn: 115477
2010-10-03 20:23:13 +00:00
d3593c3a8e
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
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llvm-svn: 115473
2010-10-03 19:09:13 +00:00
66e08d43d2
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
b44b202d66
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
3a0a620c2e
what the heck, add support for the rest of the 3dNow! binary operations.
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llvm-svn: 115467
2010-10-03 18:24:18 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
ae1a9de083
stub out a header to put 3dNow! instructions into.
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llvm-svn: 115429
2010-10-02 23:06:23 +00:00
4756bbeba0
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
0e854f3d43
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
14e909a942
Delete token *after* reading from it.
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llvm-svn: 115311
2010-10-01 12:25:27 +00:00
dd224d2333
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
c6e13f7383
Clean up asm writer usage for x86 and msp430 to flag that the writer should
...
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
2010-09-30 23:40:25 +00:00
73a7caee4b
preemptively add the rest of the non-n fpstack instructions.
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llvm-svn: 115168
2010-09-30 17:11:29 +00:00
4373badcdf
implement support for finit, PR8258
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llvm-svn: 115156
2010-09-30 16:42:53 +00:00
adc0dbe470
add support for fstcw, PR8259
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llvm-svn: 115154
2010-09-30 16:39:29 +00:00
bad267fa05
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
70d6e0e0ff
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
0574cc556a
Noticed by inspection when looking for other cmov bits.
...
llvm-svn: 115100
2010-09-29 23:00:29 +00:00
23ebf4b319
Add parens to fix GCC warning:
...
lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
llvm-svn: 115064
2010-09-29 18:56:57 +00:00
2b43c1cf42
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
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llvm-svn: 115061
2010-09-29 18:39:16 +00:00
8f7851d2b4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
...
llvm-svn: 115029
2010-09-29 05:05:03 +00:00
52e6020883
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
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llvm-svn: 115027
2010-09-29 04:55:40 +00:00
5da7f9fcfd
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
...
order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
a4e1c74947
implement support for 32-bit address operands in 64-bit mode, which
...
are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
f60062fd55
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
ff3a3930a0
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
...
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
ef1c2fc305
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
...
llvm-svn: 115017
2010-09-29 02:24:57 +00:00
a63292a3ca
implement rdar://8456378 and PR7557 - support for the fstsw,
...
an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
b44fd24fc1
change the protocol TargetAsmPArser::MatchInstruction method to take an
...
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
786874de82
MMX parameters aren't handled here yet.
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llvm-svn: 114844
2010-09-27 17:29:47 +00:00
b6a7f97c88
yet more aliases.
...
llvm-svn: 114822
2010-09-27 07:24:57 +00:00
882626cd5b
add a couple more aliases, rdar://8456378
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llvm-svn: 114821
2010-09-27 07:21:41 +00:00
972c60d821
fix rdar://8470918 - llvm-mc can't assemble smovl
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llvm-svn: 114819
2010-09-27 07:11:53 +00:00
ff0062af62
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
...
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
b5b71e07af
improve indentation
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llvm-svn: 114815
2010-09-27 06:34:01 +00:00
422e463be7
This code should never fire on non-darwin subtargets.
...
llvm-svn: 114811
2010-09-27 06:01:51 +00:00
4f59cbfb66
implement support for 'clr' alias. This is part of rdar://8416805,
...
but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
75d65b9a03
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
...
symbols defined in merge sections in independent atoms.
llvm-svn: 114786
2010-09-25 05:42:19 +00:00
6a4cd59b08
We can't return SSE/MMX vectors if SSE is disabled.
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llvm-svn: 114745
2010-09-24 19:05:48 +00:00
2c5df619c4
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
bd57e0ce3d
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
Chris Lattner