Commit Graph

416 Commits

Author SHA1 Message Date
Eugene Leviant 99da752980 [ELF/AArch64] Implement some UABS relocs
Differential revision: https://reviews.llvm.org/D24403

llvm-svn: 281202
2016-09-12 10:02:41 +00:00
Simon Atanasyan 643729d277 [ELF][MIPS] Support R_MIPS_TLS_DTPREL64 / R_MIPS_TLS_TPREL64 relocations calculation
llvm-svn: 280666
2016-09-05 15:42:43 +00:00
Simon Atanasyan 875951eceb [ELF][MIPS] Support R_MIPS_TLS_DTPREL32 / R_MIPS_TLS_TPREL32 relocations calculation
llvm-svn: 280665
2016-09-05 15:42:39 +00:00
Rafael Espindola 79202c378f Fix the implementation of R_386_GOTPC and R_386_GOTOFF.
They were both pointing to the start of the got, not the end.

Fixes pr28924.

llvm-svn: 280310
2016-08-31 23:24:11 +00:00
Rui Ueyama 7caf48cc5b Initialize RelativeRel for AMDGPU.
Target->RelativeRel is used for all platforms, but AMDGPU did
not send that member.

Fixes bug 30227 - RelativeRel is used, but not initialized for AMDGPU.

Differential Revision: https://reviews.llvm.org/D24100

llvm-svn: 280291
2016-08-31 21:04:25 +00:00
Simon Atanasyan e5532a12f7 [ELF][MIPS] Support R_MIPS_HIGHER / R_MIPS_HIGHEST relocations calculation
llvm-svn: 280223
2016-08-31 11:47:21 +00:00
Simon Atanasyan 97519cba2e [ELF][MIPS] Inline function. NFC
llvm-svn: 280222
2016-08-31 11:47:17 +00:00
Nico Weber d08aa5c391 fix typo "varaibles"
llvm-svn: 279638
2016-08-24 16:36:41 +00:00
Ed Schouten 21483f5636 Add R_386_TLS_LE as a relocation having an implicit addend.
TLS on i386 in non-PIE/PIC code seems broken right now, because we don't
properly add the addend encoded in the instruction to the resulting
offset when processing R_386_TLS_LE relocations.

Extend one of the existing tests for TLS on i686 to use an addend.

PR:		https://llvm.org/bugs/show_bug.cgi?id=29068
Reviewed by:	ruiu
Differential Revision:	https://reviews.llvm.org/D23741

llvm-svn: 279368
2016-08-20 10:54:51 +00:00
Simon Atanasyan 978f91ca43 [ELF][MIPS] Support R_MIPS_GOT_HI16 / R_MIPS_GOT_LO16 relocations calculation
llvm-svn: 279119
2016-08-18 19:08:41 +00:00
Simon Atanasyan e933a8e212 [ELF][MIPS] Support R_MIPS_CALL_HI16 / R_MIPS_CALL_LO16 relocations calculation
llvm-svn: 279118
2016-08-18 19:08:36 +00:00
Michael J. Spencer e2cc07bc0b [ELF] Set MAXPAGESIZE to 2MiB on x86-64 to match bfd and gold.
The FreeBSD kernel relies on this behavior to not overwrite the boot loader.

llvm-svn: 278889
2016-08-17 02:10:51 +00:00
Rui Ueyama 6c50990df6 Add EM_IAMCU support.
This patch adds "-m elf_iamcu" to ldd for IAMCU psABI:
https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI

Patch by H.J Lu.

llvm-svn: 277643
2016-08-03 20:15:56 +00:00
Davide Italiano 38115ffcef [ELF/ARM] Add support for R_ARM_TARGET1 relocation.
Differential Revision:  https://reviews.llvm.org/D22990

llvm-svn: 277369
2016-08-01 19:28:13 +00:00
Simon Atanasyan d2ae303eb0 [ELF][MIPS] Apply mask while reading implicit addend and writing result of R_MIPS_26 relocation.
llvm-svn: 276395
2016-07-22 05:56:43 +00:00
Konstantin Zhuravlyov 667e245e38 ELF/AMDGPU: Add support for R_AMDGPU_ABS32
Differential Revision: https://reviews.llvm.org/D21654

llvm-svn: 276295
2016-07-21 15:30:13 +00:00
Simon Atanasyan a088bce959 [ELF][MIPS] Create PLT entry specific for MIPS ABI version R6
llvm-svn: 276173
2016-07-20 20:15:33 +00:00
Rafael Espindola 0f7cedaa1e Create thunks before regular relocation scan.
We will need to do something like this to support range extension
thunks since that process is iterative.

Doing this also has the advantage that when doing the regular
relocation scan the offset in the output section is known and we can
just store that. This reduces the number of times we have to run
getOffset and I think will allow a more specialized .eh_frame
representation.

By itself this is already a performance win.

firefox
  master 7.295045737
  patch  7.209466989 0.98826892235
chromium
  master 4.531254468
  patch  4.509221804 0.995137623774
chromium fast
  master 1.836928973
  patch  1.823805241 0.992855612714
the gold plugin
  master 0.379768791
  patch  0.380043405 1.00072310839
clang
  master 0.642698284
  patch  0.642215663 0.999249070657
llvm-as
  master 0.036665467
  patch  0.036456225 0.994293213284
the gold plugin fsds
  master 0.40395817
  patch  0.404384555 1.0010555177
clang fsds
  master 0.722045545
  patch  0.720946135 0.998477367518
llvm-as fsds
  master 0.03292646
  patch  0.032759965 0.994943428477
scylla
  master 3.427376378
  patch  3.368316181 0.98276810292

llvm-svn: 276146
2016-07-20 17:58:07 +00:00
Peter Smith 441cf5d818 Initial support for the local dynamic model ARM TLS relocations:
- R_ARM_TLS_LDM32
- R_ARM_TLS_LDO32

The local dynamic implementation and tests follows the same model as 
the other ARM TLS models. The R_ARM_TLS_LDO32 is implemented as R_ABS 
expr type as the getVA() for a TLS symbol will return the offset from the 
start of the TLS block.

Differential Revision https://reviews.llvm.org/D22563
 

llvm-svn: 276123
2016-07-20 14:56:26 +00:00
Peter Smith 9d450256d2 Support for standard model ARM TLS
Add relocations and identification functions for the Initial Exec
and Global Dynamic TLS model defined in Addenda to, and Errata in,
the ABI for the ARM Architecture.
    
ARM uses variant 1 of the thread local storage data
structures as defined in ELF Handling for Thread-Local Storage.
    
The "experimental" descriptor based model that can be selected in
gcc, but not clang with -mtls-dialect=gnu2 is not supported.
    
The relocations R_ARM_TLS_LE12 and R_ARM_TLS_IE12GP are not
supported, I know of no ARM Toolchain that supports these relocations
as they limit the size of the TLS block.
    
No code relaxation is supported as the standard ARM TLS model puts
the relocations on literal data.
    
Support for the local dynamic model will come in a follow up patch.

Differential Revision: https://reviews.llvm.org/D22462

llvm-svn: 276095
2016-07-20 08:52:27 +00:00
Rui Ueyama 941faa77ad Remove TargetInfo::getImageBase. NFC.
llvm-svn: 275447
2016-07-14 17:43:28 +00:00
Rui Ueyama 0fad6ea551 Attempt to unbreak msan bot.
r275301 made .got section be aligned on Target->GotEntrySize,
so GotEntrySize must have been initialized. We didn't initialize
it for AMDGPU.

llvm-svn: 275373
2016-07-14 05:46:22 +00:00
Rui Ueyama 803b120ba1 Add GotEntrySize/GotPltEntrySize to ELF target.
Patch by H.J Lu.

For x86-64 psABI, the entry size of .got and .got.plt sections is 8
bytes for both LP64 and ILP32.  Add GotEntrySize and GotPltEntrySize
to ELF target instead of using size of ELFT::uint.  Now we can generate
a simple working x32 executable.

Differential Revision: http://reviews.llvm.org/D22288

llvm-svn: 275301
2016-07-13 18:55:14 +00:00
Rui Ueyama 484a49514f Rename VAStart -> ImageBase. NFC.
Config members are named after corresponding command line options.
This patch renames VAStart ImageBase so that they are in line with
--image-base.

Differential Revision: http://reviews.llvm.org/D22277

llvm-svn: 275298
2016-07-13 18:40:59 +00:00
Rui Ueyama 46626e1f04 Add ILP32 support to X86_64TargetInfo.
Patch by H.J. Lu.

As x86-64 psABI supports both LP64 and ILP32, this patch adds <ELFT>
template to X86_64TargetInfo.

Differential Revision: http://reviews.llvm.org/D22287

llvm-svn: 275235
2016-07-12 23:28:31 +00:00
Rui Ueyama e2efadced7 Remove Target::writeThunk.
Only MipsThunk were using the function, and the way how it wrote
thunk contents was different from ARM thunks. This patch makes
them consistent.

llvm-svn: 274997
2016-07-09 22:52:32 +00:00
Peter Smith fb05cd997c Recommit R274836 Add Thunk support framework for ARM and Mips
The TinyPtrVector of const Thunk<ELFT>* in InputSections.h can cause 
build failures on certain compiler/library combinations when Thunk<ELFT> 
is not a complete type or is an abstract class. Fixed by making Thunk<ELFT>
non Abstract.

type or is an abstract class 

llvm-svn: 274863
2016-07-08 16:10:27 +00:00
Peter Smith eeb827447e Revert R274836 Add Thunk support framework for ARM and Mips
This seems to be causing a buildbot failure on lld-x86_64-freebsd. Will
reproduce locally and fix. 

llvm-svn: 274841
2016-07-08 12:25:50 +00:00
Peter Smith de01b98a26 Add Thunk support framework for ARM and Mips
Generalise the Mips LA25 Thunk code and implement ARM and Thumb
    interworking Thunks.
    
    - Introduce a new module Thunks.cpp to store the Target Specific Thunk
      implementations.
    - DefinedRegular and Shared have a ThunkData field to record Thunk.
    - A Target can have more than one type of Thunk.
    - Support PC-relative calls to Thunks.
    - Support Thunks to PLT entries.
    - Existing Mips LA25 Thunk code integrated.
    - Support for ARMv7A interworking Thunks.
    
    Limitations:
    - Only one Thunk per SymbolBody, this is sufficient for all currently
      implemented Thunks.
    - ARM thunks assume presence of V6T2 MOVT and MOVW instructions.

    Differential revision: http://reviews.llvm.org/D21891

llvm-svn: 274836
2016-07-08 11:13:40 +00:00
Rafael Espindola 9639ec1e66 Read the implicit addend of R_386_GOT32X.
llvm-svn: 274690
2016-07-06 21:48:50 +00:00
Rafael Espindola d03e659140 Recognize R_386_GOT32X.
We don't relax it, but we at least recognize it.

llvm-svn: 274687
2016-07-06 21:41:39 +00:00
Tom Stellard 391e3a873e ELF/AMDGPU: Add support for GOT relocations
Reviewers: arsenm, rafael, tony-tye, kzhuravl, ruiu

Subscribers: llvm-commits, kzhuravl

Differential Revision: http://reviews.llvm.org/D21481

llvm-svn: 274514
2016-07-04 19:19:07 +00:00
Simon Atanasyan 002e244717 [ELF][MIPS] Support MIPS TLS relocations
The patch adds one more partition to the MIPS GOT. This time it is for
TLS related GOT entries. Such entries are located after 'local' and 'global'
ones. We cannot get a final offset for these entries at the time of
creation because we do not know size of 'local' and 'global' partitions.
So we have to adjust the offset later using `getMipsTlsOffset()` method.

All MIPS TLS relocations which need GOT entries operates MIPS style GOT
offset - 'offset from the GOT's beginning' - MipsGPOffset constant. That
is why I add new types of relocation expressions.

One more difference from othe ABIs is that the MIPS ABI does not support
any TLS relocation relaxations. I decided to make a separate function
`handleMipsTlsRelocation` and put MIPS TLS relocation handling code
there. It is similar to `handleTlsRelocation` routine and duplicates its
code. But it allows to make the code cleaner and prevent pollution of
the `handleTlsRelocation` by MIPS 'if' statements.

Differential Revision: http://reviews.llvm.org/D21606

llvm-svn: 273569
2016-06-23 15:26:31 +00:00
Rui Ueyama 39061a5220 Simplify writeThunk. NFC.
Previously, `Buf + 4` was written twice.

llvm-svn: 273337
2016-06-21 23:53:08 +00:00
Rui Ueyama 03a6cec51e Detect invalid use of R_X86_64_GOTTPOFF.
It is an ABI requirement that the relocation must be used
in MOVQ or LEAQ instructions. Previously, we ignored invalid
relocations.

llvm-svn: 273248
2016-06-21 06:03:28 +00:00
Rui Ueyama b319ae2cf1 Refactor X86TargetInfo::relaxTlsIeToLe.
`Inst` and `Op` variables are removed since they are not always
point to an instruction nor an operand. For 5-byte MOV instruction,
Op points to an instruction, which is confusing.

llvm-svn: 273246
2016-06-21 05:44:14 +00:00
Rui Ueyama 73575c4d5e Fix typo in comment.
llvm-svn: 273243
2016-06-21 05:09:39 +00:00
Rui Ueyama 3f5dd1458e Unbreak buildbots.
llvm-svn: 273242
2016-06-21 05:01:31 +00:00
Rui Ueyama 55a9def2bf Refactor X86_64TargetInfo::relaxTlsIeToLe.
This patch is to rewrite the function with a table-lookup-ish approach
so that it can read as a series of "convert this pattern to this" pattern.

llvm-svn: 273238
2016-06-21 03:42:32 +00:00
Tom Stellard 1cfb9efdf7 ELF/AMDGPU: Add support for R_AMDGPU_REL32 relocations
Reviewers: rafael, ruiu

Subscribers: kzhuravl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21294

llvm-svn: 273192
2016-06-20 19:48:29 +00:00
Simon Atanasyan 4132511cdc [ELF][MIPS] Support GOT entries for non-preemptible symbols with different addends
There are two motivations for this patch. The first one is a preparation
for support MIPS TLS relocations. It might sound like a joke but for GOT
entries related to TLS relocations MIPS ABI uses almost regular approach
with creation of dynamic relocations for each GOT enty etc. But we need
to separate these 'regular' TLS related entries from MIPS specific local
and global parts of GOT. ABI declare simple solution - all TLS related
entries allocated at the end of GOT after local/global parts. The second
motivation it to support GOT relocations for non-preemptible symbols
with addends. If we have more than one GOT relocations against symbol S
with different addends we need to create GOT entries for each unique
Symbol/Addend pairs.

So we store all MIPS GOT entries in separate containers. For non-preemptible
symbols we have to maintain two data structures. The first one is MipsLocal
vector. Each entry corresponds to the GOT entry from the 'local' part
of the GOT contains the symbol's address plus addend. The second one
is MipsLocalMap. It is a map from Symbol/Addend pair to the GOT index.

Differential Revision: http://reviews.llvm.org/D21297

llvm-svn: 273127
2016-06-19 21:39:37 +00:00
Rui Ueyama c737ef5d21 Remove default values that vary depending on target.
llvm-svn: 272976
2016-06-16 23:50:25 +00:00
Rui Ueyama 2f524fb7c7 Make a switch-case a function for the sake of simplicity.
llvm-svn: 272975
2016-06-16 23:28:08 +00:00
Rui Ueyama e991a49587 Merge cases that execute the same code.
llvm-svn: 272974
2016-06-16 23:28:06 +00:00
Rui Ueyama a71ba43ed3 Early return. NFC.
llvm-svn: 272973
2016-06-16 23:28:05 +00:00
Rui Ueyama bebf4897a3 Simplify. NFC.
llvm-svn: 272972
2016-06-16 23:28:03 +00:00
Rui Ueyama 595bc5db4b Simplify *(x+y) to x[y]. NFC.
They are equivalent in C (and in C++ in this case).

llvm-svn: 272942
2016-06-16 19:48:07 +00:00
Rui Ueyama 727cd2f73f Simplify. NFC.
llvm-svn: 272924
2016-06-16 17:18:25 +00:00
Rui Ueyama e517de655b Inline a small function. NFC.
llvm-svn: 272923
2016-06-16 17:06:24 +00:00
Rui Ueyama f9d5620029 Early return. NFC.
llvm-svn: 272917
2016-06-16 16:44:52 +00:00