Commit Graph

218047 Commits

Author SHA1 Message Date
Richard Trieu fc69e7d65b Cast variable to void to resolve unused variable warning in non-asserts builds.
llvm-svn: 255704
2015-12-15 23:25:34 +00:00
Hans Wennborg 7036e503d7 Fix "Not having LAHF/SAHF" assert.
It wants to assert that the subtarget is 64-bit, not the register.

llvm-svn: 255703
2015-12-15 23:21:46 +00:00
Tom Stellard 7750f4ed9e AMDGPU/SI: Set the code object work group segment size when targeting HSA
Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15493

llvm-svn: 255702
2015-12-15 23:15:25 +00:00
Davide Italiano 3eb47e223e [llvm-objdump/MachODump] Shrink code a little bit. NFC.
llvm-svn: 255701
2015-12-15 23:14:21 +00:00
Sanjay Patel 271efcdf20 [x86] inline calls to fmaxf / llvm.maxnum.f32 using maxss (PR24475)
This patch improves on the suggested codegen from PR24475:
https://llvm.org/bugs/show_bug.cgi?id=24475

but only for the fmaxf() case to start, so we can sort out any bugs before
extending to fmin, f64, and vectors.

The fmax / maxnum definitions provide us flexibility for signed zeros, so the
only thing we have to worry about in this replacement sequence is NaN handling.

Note 1: It may be better to implement this as lowerFMAXNUM(), but that exposes
a problem: SelectionDAGBuilder::visitSelect() transforms compare/select
instructions into FMAXNUM nodes if we declare FMAXNUM legal or custom. Perhaps
that should be checking for NaN inputs or global unsafe-math before transforming?
As it stands, that bypasses a big set of optimizations that the x86 backend 
already has in PerformSELECTCombine().

Note 2: The v2f32 test reveals another bug; the vector is extended to v4f32, so
we have completely unnecessary operations happening on undef elements of the 
vector.

Differential Revision: http://reviews.llvm.org/D15294

llvm-svn: 255700
2015-12-15 23:11:43 +00:00
James Y Knight 99fcb721b2 [Sparc] Tweak r255668: Use llvm_unreachable.
llvm-svn: 255698
2015-12-15 23:07:16 +00:00
Greg Clayton 0817da881e First pass at LLDBRPC.framework
llvm-svn: 255697
2015-12-15 23:03:22 +00:00
Enrico Granata 935f31cbc0 Add a few common paths that are not to be tracked to the svnignore property
llvm-svn: 255696
2015-12-15 23:01:30 +00:00
Evgeniy Stepanov da1cf9287c Cross-DSO control flow integrity (compiler-rt part).
This is an initial version of the runtime cross-DSO CFI support
library.

It contains a number of FIXMEs, ex. it does not support the
diagnostic mode nor dlopen/dlclose, but it works and can be tested.
Diagnostic mode, in particular, would require some refactoring (we'd
like to gather all CFI hooks in the UBSan library into one function
so that we could easier pass the diagnostic information down to
__cfi_check). It will be implemented later.

Once the diagnostic mode is in, I plan to create a second test
configuration to run all existing tests in both modes. For now, this
patch includes only a few new cross-DSO tests.

llvm-svn: 255695
2015-12-15 23:00:33 +00:00
Evgeniy Stepanov fd6f92d5cb Cross-DSO control flow integrity (Clang part).
Clang-side cross-DSO CFI.

* Adds a command line flag -f[no-]sanitize-cfi-cross-dso.
* Links a runtime library when enabled.
* Emits __cfi_slowpath calls is bitset test fails.
* Emits extra hash-based bitsets for external CFI checks.
* Sets a module flag to enable __cfi_check generation during LTO.

This mode does not yet support diagnostics.

llvm-svn: 255694
2015-12-15 23:00:20 +00:00
Evgeniy Stepanov 67849d56c3 Cross-DSO control flow integrity (LLVM part).
An LTO pass that generates a __cfi_check() function that validates a
call based on a hash of the call-site-known type and the target
pointer.

llvm-svn: 255693
2015-12-15 23:00:08 +00:00
Tom Stellard a495307e5e AMDGPU/SI: Set the code objects private segment size when targeting HSA.
Summary: I'm not sure how things worked before without this.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15492

llvm-svn: 255692
2015-12-15 22:55:30 +00:00
Cong Hou a73ffa2206 [LoopVectorizer] Refine loop vectorizer's register usage calculator by ignoring specific instructions.
(This is the third attempt to check in this patch, and the first two are r255454
and r255460. The once failed test file reg-usage.ll is now moved to
test/Transform/LoopVectorize/X86 directory with target datalayout and target
triple indicated.)

LoopVectorizationCostModel::calculateRegisterUsage() is used to estimate the
register usage for specific VFs. However, it takes into account many
instructions that won't be vectorized, such as induction variables,
GetElementPtr instruction, etc.. This makes the loop vectorizer too conservative
when choosing VF. In this patch, the induction variables that won't be
vectorized plus GetElementPtr instruction will be added to ValuesToIgnore set
so that their register usage won't be considered any more.


Differential revision: http://reviews.llvm.org/D15177

llvm-svn: 255691
2015-12-15 22:45:09 +00:00
NAKAMURA Takumi db87d5dbfd clang/test/CodeGen/ms_this.cpp: Fix for -Asserts.
llvm-svn: 255690
2015-12-15 22:42:28 +00:00
Tom Stellard 29dd05e92f AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA
Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15426

llvm-svn: 255689
2015-12-15 22:39:36 +00:00
Xinliang David Li 1fbae3b76a [PGO] Improve prof library portability
Patch by: Johan Engelen

Introduce LLVM_LIBRARY_WEAK macro. Define LLVM_LIBRARY_WEAK
and LLVM_LIBRARY_VISIBIITY for MSVC

llvm-svn: 255688
2015-12-15 22:38:18 +00:00
Enrico Granata f85b008de8 Enable the 'type X list' formatters commands to list formatters in language categories
llvm-svn: 255687
2015-12-15 22:20:19 +00:00
Eric Fiselier 8087ddd1e6 Remove unused _LIBCPP_HAS_NO_ALWAYS_INLINE_VARIADICS macro
llvm-svn: 255686
2015-12-15 22:19:03 +00:00
NAKAMURA Takumi 512bd57699 Fix clang/test/CodeGen/ms_this.cpp.
llvm-svn: 255685
2015-12-15 22:19:00 +00:00
Xinliang David Li be49271399 [PGO] Open file with explict binary mode
Patch by: Johan Engelen

On windows, opening in text mode will result in
line ending chars to be appended leading to
profile corruption.

llvm-svn: 255684
2015-12-15 22:18:11 +00:00
Eric Fiselier 8dcfcf79ab [libcxx] Enable noexcept for GCC 4.6 and greater
Summary:
This patch allows GCC 4.6 and above to use `noexcept` as opposed to `throw()`. 

Is it an ABI safe change to suddenly switch on `noexcept`? I imagine it must be because it's disabled in w/ clang in C++03 but not C++11.


Reviewers: danalbert, jroelofs, mclow.lists

Subscribers: cfe-commits

Differential Revision: http://reviews.llvm.org/D15516

llvm-svn: 255683
2015-12-15 22:16:47 +00:00
Reid Kleckner 3ecc84afb3 Wrap include of <future> in some warning suppression pragmas
Eventually we may need to sink this include to the .cpp file or
something to suport LLVM_ENABLE_THREADS=OFF, but this solves my
immediate problem of fixing the build.

llvm-svn: 255682
2015-12-15 22:10:30 +00:00
Dan Gohman 4b9d7916ee [WebAssembly] Implement instruction selection for constant offsets in addresses.
Add instruction patterns for matching load and store instructions with constant
offsets in addresses. The code is fairly redundant due to the need to replicate
everything between imm, tglobaldadr, and texternalsym, but this appears to be
common tablegen practice. The main alternative appears to be to introduce
matching functions with C++ code, but sticking with purely generated matchers
seems better for now.

Also note that this doesn't yet support offsets from getelementptr, which will
be the most common case; that will depend on a change in target-independent code
in order to set the NoUnsignedWrap flag, which I'll submit separately. Until
then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add.

Also implement isLegalAddressingMode with an approximation of this.

Differential Revision: http://reviews.llvm.org/D15538

llvm-svn: 255681
2015-12-15 22:01:29 +00:00
Xinliang David Li 38b9a32fcd Initialize all bytes in vp data (msan error)
llvm-svn: 255680
2015-12-15 21:57:08 +00:00
Eric Christopher 5f97bbaa9c Add support for the .debug_macro section of the forthcoming DWARF 5 spec.
Patch by B. Sivachandra Reddy!

llvm-svn: 255679
2015-12-15 21:50:27 +00:00
Reid Kleckner b6dfee2d73 Fix clang-cl self-host with MSVC 2013 STL std::bind implementation
llvm-svn: 255678
2015-12-15 21:41:58 +00:00
Reid Kleckner d7045faa10 [WinEH] Remove unused intrinsic llvm.x86.seh.restoreframe
We can clean this up now that we have the X86 CATCHRET instruction to
restore the FP, SP, and BP.

llvm-svn: 255677
2015-12-15 21:41:34 +00:00
Todd Fiala 6d3de12315 test-infra: refactored new summary results into base ResultsFormatter class
This allows more specialized formatters to still reuse the results
summarization display from the base class.

llvm-svn: 255676
2015-12-15 21:33:38 +00:00
David Majnemer 0b17d44faf [WinEH] Update clang to use operand bundles on call sites
This updates clang to use bundle operands to associate an invoke with
the funclet which it is contained within.

Depends on D15517.

Differential Revision: http://reviews.llvm.org/D15518

llvm-svn: 255675
2015-12-15 21:27:59 +00:00
David Majnemer 3bb88c0210 [WinEH] Use operand bundles to describe call sites
SimplifyCFG allows tail merging with code which terminates in
unreachable which, in turn, makes it possible for an invoke to end up in
a funclet which it was not originally part of.

Using operand bundles on invokes allows us to determine whether or not
an invoke was part of a funclet in the source program.

Furthermore, it allows us to unambiguously answer questions about the
legality of inlining into call sites which the personality may have
trouble with.

Differential Revision: http://reviews.llvm.org/D15517

llvm-svn: 255674
2015-12-15 21:27:27 +00:00
Xinliang David Li 2a27fc40a8 Test cleanup -- remove duplicate run lines
llvm-svn: 255673
2015-12-15 21:15:06 +00:00
Tom Stellard a6f24c6565 AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions
Summary:
We were previously selecting all constant loads to SMRD instructions and legalizing
the SMRDs with non-uniform addresses during the SIFixSGPRCopesPass.

This new solution is more simple and also generates much better code, because
the instruction selector is able to take advantage of all the MUBUF addressing
modes that are legalization pass wasn't able to.

We also no longer need to generate v_add_* instructions when we
have a uniform pointer and a non-uniform offset, as this is now folded into the
MUBUF instruction during instruction selection.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15425

llvm-svn: 255672
2015-12-15 20:55:55 +00:00
Alex Denisov 596e97924a LLVM tutorial: fix broken links/anchors
llvm-svn: 255671
2015-12-15 20:50:29 +00:00
Xinliang David Li 4ec401406e Coverage code refactoring /NFC
llvm-svn: 255670
2015-12-15 19:44:45 +00:00
Justin Bogner 843fb204b7 LPM: Stop threading `Pass *` through all of the loop utility APIs. NFC
A large number of loop utility functions take a `Pass *` and reach
into it to find out which analyses to preserve. There are a number of
problems with this:

- The APIs have access to pretty well any Pass state they want, so
  it's hard to tell what they may or may not do.

- Other APIs have copied these and pass around a `Pass *` even though
  they don't even use it. Some of these just hand a nullptr to the API
  since the callers don't even have a pass available.

- Passes in the new pass manager don't work like the current ones, so
  the APIs can't be used as is there.

Instead, we should explicitly thread the analysis results that we
actually care about through these APIs. This is both simpler and more
reusable.

llvm-svn: 255669
2015-12-15 19:40:57 +00:00
James Y Knight 33beb24318 [Sparc] Fix handling of double incoming arguments on sparc little-endian.
On SparcV8, doubles get passed in two 32-bit integer registers. The call
code was already handling endianness correctly, but the incoming
argument code was not -- it got the two halves in opposite order.

Also remove some dead code in LowerFormalArguments_32 to handle
less-than-32bit values, which can't actually happen.

Finally, add some test cases for the 32-bit calling convention, cribbed
from the 64abi.ll test, and run for both big and little-endian.

llvm-svn: 255668
2015-12-15 19:23:12 +00:00
Krzysztof Parzyszek 6c3b837452 Unsupport test that should not be run on Hexagon
llvm-svn: 255667
2015-12-15 19:14:24 +00:00
Akira Hatanaka a84428e687 [Docs] Fix Unexpected indentation errors.
llvm-svn: 255665
2015-12-15 19:11:48 +00:00
Michael Kuperstein 53946bf8c6 [X86] MOVPC32r should only emit CFI adjustments when needed
We only want to emit CFI adjustments when actually using DWARF.
This fixes PR25828.

Differential Revision: http://reviews.llvm.org/D15522

llvm-svn: 255664
2015-12-15 18:50:32 +00:00
Tom Stellard 0abd28140b AMDGPU: Add aliases for all VI targets
llvm-svn: 255663
2015-12-15 18:37:04 +00:00
Tom Stellard 655680a22b AMDGPU: Add alias for tonga
Patch by: Vedran Mileti

llvm-svn: 255662
2015-12-15 18:37:02 +00:00
Tom Stellard dbe374b2c5 AMDGPU/SI: Implement AMDGPUTargetTransformInfo::isSourceOfDivergence()
Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15476

llvm-svn: 255661
2015-12-15 18:04:38 +00:00
Sanjay Patel 38a022623a [SimplifyCFG] allow speculation of exactly one expensive instruction (PR24818)
This is the last general step to allow more IR-level speculation with a safety harness in place in CodeGenPrepare.

The intent is to restore the behavior enabled by:
http://reviews.llvm.org/rL228826

but prevent bad performance such as:
https://llvm.org/bugs/show_bug.cgi?id=24818

Earlier patches in this sequence:
D12882 (disable SimplifyCFG speculation for expensive instructions)
D13297 (have CGP despeculate expensive ops)
D14630 (have CGP despeculate special versions of cttz/ctlz)

As shown in the test cases, we only have two instructions currently affected: ctz for some x86 and fdiv generally. 
Allowing exactly one expensive instruction is a bit of a hack, but it lines up with what is currently implemented
in CGP. If we make the despeculation more general in CGP, we can make the speculation here more liberal.

A follow-up patch will adjust the cost for sqrt and possibly other typically expensive math intrinsics (currently
everything is cheap by default). GPU targets would likely want to override those expensive default costs (just as
they probably should already override the cost of div/rem) because just about any math is cheaper than control-flow
on those targets.

Differential Revision: http://reviews.llvm.org/D15213

llvm-svn: 255660
2015-12-15 17:38:29 +00:00
Nathan Slingerland 7f5b47ddd4 [llvm-profdata] Add support for weighted merge of profile data (2nd try)
Summary:
This change adds support for specifying a weight when merging profile data with the llvm-profdata tool.
Weights are specified by using the --weighted-input=<weight>,<filename> option. Input files not specified
with this option (normal positional list after options) are given a default weight of 1.

Adding support for arbitrary weighting of input profile data allows for relative importance to be placed on the
input data from multiple training runs.

Both sampled and instrumented profiles are supported.

Reviewers: davidxl, dnovillo, bogner, silvas

Subscribers: silvas, davidxl, llvm-commits

Differential Revision: http://reviews.llvm.org/D15306

llvm-svn: 255659
2015-12-15 17:37:09 +00:00
Nicolai Hahnle 78fd4f087b AMDGPU: mark ldexp LibCalls as unavailable
Summary:
The LibCallSimplifier will turn llvm.exp2.* intrinsics into ldexp* libcalls
which do not make sense with the AMDGPU backend.

In the long run, we'll want an llvm.ldexp.* intrinsic to properly make use of
this optimization, but this works around the problem for now.

See also: http://reviews.llvm.org/D14327 (suggested llvm.ldexp.* implementation)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709

Reviewers: arsenm, tstellarAMD

Differential Revision: http://reviews.llvm.org/D14990

llvm-svn: 255658
2015-12-15 17:24:15 +00:00
Tom Stellard 8f307217c3 AMDGPU/SI: Fix bitcast between v2f32 and f64
The radeonsi fp64 support can hit these now that some redundant bitcasts
are folded.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 255657
2015-12-15 17:11:17 +00:00
Hans Wennborg 08d5905bac [X86] Smaller code for materializing 32-bit 1 and -1 constants
"movl $-1, %eax" is 5 bytes, "xorl %eax, %eax; decl %eax" is 3 bytes.
This commit makes LLVM use the latter when optimizing for size.

Differential Revision: http://reviews.llvm.org/D14971

llvm-svn: 255656
2015-12-15 17:10:28 +00:00
Nico Weber 0d10b2cf3c clang-cl: Add an alias for /wd4100
llvm-svn: 255655
2015-12-15 17:07:16 +00:00
JF Bastien dac806c783 WebAssembly: update expected torture test failures
We now have 252 expected failures.

llvm-svn: 255654
2015-12-15 17:07:07 +00:00
Krzysztof Parzyszek 372bd80834 [Hexagon] Preprocess mapped instructions before lowering to MC
llvm-svn: 255653
2015-12-15 17:05:45 +00:00