forked from OSchip/llvm-project
300 lines
9.6 KiB
C++
300 lines
9.6 KiB
C++
//===--- Mips.cpp - Implement Mips target feature support -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements Mips TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "Mips.h"
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#include "Targets.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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const Builtin::Info MipsTargetInfo::BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
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#define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
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{#ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr},
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#include "clang/Basic/BuiltinsMips.def"
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};
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bool MipsTargetInfo::processorSupportsGPR64() const {
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return llvm::StringSwitch<bool>(CPU)
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.Case("mips3", true)
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.Case("mips4", true)
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.Case("mips5", true)
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.Case("mips64", true)
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.Case("mips64r2", true)
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.Case("mips64r3", true)
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.Case("mips64r5", true)
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.Case("mips64r6", true)
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.Case("octeon", true)
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.Case("octeon+", true)
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.Default(false);
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return false;
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}
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static constexpr llvm::StringLiteral ValidCPUNames[] = {
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{"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
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{"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
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{"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
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{"octeon"}, {"octeon+"}, {"p5600"}};
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bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
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}
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void MipsTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
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}
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unsigned MipsTargetInfo::getISARev() const {
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return llvm::StringSwitch<unsigned>(getCPU())
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.Cases("mips32", "mips64", 1)
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.Cases("mips32r2", "mips64r2", "octeon", "octeon+", 2)
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.Cases("mips32r3", "mips64r3", 3)
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.Cases("mips32r5", "mips64r5", 5)
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.Cases("mips32r6", "mips64r6", 6)
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.Default(0);
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}
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void MipsTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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if (BigEndian) {
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DefineStd(Builder, "MIPSEB", Opts);
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Builder.defineMacro("_MIPSEB");
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} else {
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DefineStd(Builder, "MIPSEL", Opts);
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Builder.defineMacro("_MIPSEL");
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}
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Builder.defineMacro("__mips__");
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Builder.defineMacro("_mips");
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if (Opts.GNUMode)
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Builder.defineMacro("mips");
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if (ABI == "o32") {
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Builder.defineMacro("__mips", "32");
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Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
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} else {
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Builder.defineMacro("__mips", "64");
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Builder.defineMacro("__mips64");
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Builder.defineMacro("__mips64__");
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Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
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}
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const std::string ISARev = std::to_string(getISARev());
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if (!ISARev.empty())
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Builder.defineMacro("__mips_isa_rev", ISARev);
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if (ABI == "o32") {
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Builder.defineMacro("__mips_o32");
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Builder.defineMacro("_ABIO32", "1");
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Builder.defineMacro("_MIPS_SIM", "_ABIO32");
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} else if (ABI == "n32") {
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Builder.defineMacro("__mips_n32");
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Builder.defineMacro("_ABIN32", "2");
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Builder.defineMacro("_MIPS_SIM", "_ABIN32");
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} else if (ABI == "n64") {
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Builder.defineMacro("__mips_n64");
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Builder.defineMacro("_ABI64", "3");
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Builder.defineMacro("_MIPS_SIM", "_ABI64");
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} else
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llvm_unreachable("Invalid ABI.");
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if (!IsNoABICalls) {
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Builder.defineMacro("__mips_abicalls");
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if (CanUseBSDABICalls)
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Builder.defineMacro("__ABICALLS__");
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}
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Builder.defineMacro("__REGISTER_PREFIX__", "");
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switch (FloatABI) {
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case HardFloat:
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Builder.defineMacro("__mips_hard_float", Twine(1));
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break;
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case SoftFloat:
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Builder.defineMacro("__mips_soft_float", Twine(1));
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break;
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}
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if (IsSingleFloat)
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Builder.defineMacro("__mips_single_float", Twine(1));
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switch (FPMode) {
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case FPXX:
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Builder.defineMacro("__mips_fpr", Twine(0));
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break;
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case FP32:
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Builder.defineMacro("__mips_fpr", Twine(32));
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break;
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case FP64:
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Builder.defineMacro("__mips_fpr", Twine(64));
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break;
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}
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if (FPMode == FP64 || IsSingleFloat)
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Builder.defineMacro("_MIPS_FPSET", Twine(32));
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else
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Builder.defineMacro("_MIPS_FPSET", Twine(16));
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if (IsMips16)
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Builder.defineMacro("__mips16", Twine(1));
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if (IsMicromips)
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Builder.defineMacro("__mips_micromips", Twine(1));
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if (IsNan2008)
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Builder.defineMacro("__mips_nan2008", Twine(1));
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if (IsAbs2008)
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Builder.defineMacro("__mips_abs2008", Twine(1));
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switch (DspRev) {
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default:
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break;
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case DSP1:
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Builder.defineMacro("__mips_dsp_rev", Twine(1));
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Builder.defineMacro("__mips_dsp", Twine(1));
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break;
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case DSP2:
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Builder.defineMacro("__mips_dsp_rev", Twine(2));
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Builder.defineMacro("__mips_dspr2", Twine(1));
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Builder.defineMacro("__mips_dsp", Twine(1));
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break;
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}
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if (HasMSA)
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Builder.defineMacro("__mips_msa", Twine(1));
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if (DisableMadd4)
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Builder.defineMacro("__mips_no_madd4", Twine(1));
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Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
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Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
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Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
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Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
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if (CPU == "octeon+")
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Builder.defineMacro("_MIPS_ARCH_OCTEONP");
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else
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Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
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if (StringRef(CPU).startswith("octeon"))
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Builder.defineMacro("__OCTEON__");
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// These shouldn't be defined for MIPS-I but there's no need to check
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// for that since MIPS-I isn't supported.
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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// 32-bit MIPS processors don't have the necessary lld/scd instructions
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// found in 64-bit processors. In the case of O32 on a 64-bit processor,
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// the instructions exist but using them violates the ABI since they
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// require 64-bit GPRs and O32 only supports 32-bit GPRs.
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if (ABI == "n32" || ABI == "n64")
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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}
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bool MipsTargetInfo::hasFeature(StringRef Feature) const {
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return llvm::StringSwitch<bool>(Feature)
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.Case("mips", true)
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.Case("dsp", DspRev >= DSP1)
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.Case("dspr2", DspRev >= DSP2)
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.Case("fp64", FPMode == FP64)
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.Case("msa", HasMSA)
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.Default(false);
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}
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ArrayRef<Builtin::Info> MipsTargetInfo::getTargetBuiltins() const {
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return llvm::makeArrayRef(BuiltinInfo, clang::Mips::LastTSBuiltin -
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Builtin::FirstTSBuiltin);
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}
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unsigned MipsTargetInfo::getUnwindWordWidth() const {
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return llvm::StringSwitch<unsigned>(ABI)
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.Case("o32", 32)
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.Case("n32", 64)
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.Case("n64", 64)
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.Default(getPointerWidth(0));
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}
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bool MipsTargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
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// microMIPS64R6 backend was removed.
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if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
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Diags.Report(diag::err_target_unsupported_cpu_for_micromips) << CPU;
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return false;
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}
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// FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle
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// this yet. It's better to fail here than on the backend assertion.
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if (processorSupportsGPR64() && ABI == "o32") {
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Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
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return false;
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}
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// 64-bit ABI's require 64-bit CPU's.
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if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) {
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Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU;
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return false;
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}
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// FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend
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// can't handle this yet. It's better to fail here than on the
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// backend assertion.
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if (getTriple().isMIPS64() && ABI == "o32") {
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Diags.Report(diag::err_target_unsupported_abi_for_triple)
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<< ABI << getTriple().str();
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return false;
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}
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// FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend
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// can't handle this yet. It's better to fail here than on the
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// backend assertion.
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if (getTriple().isMIPS32() && (ABI == "n32" || ABI == "n64")) {
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Diags.Report(diag::err_target_unsupported_abi_for_triple)
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<< ABI << getTriple().str();
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return false;
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}
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// -fpxx is valid only for the o32 ABI
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if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
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Diags.Report(diag::err_unsupported_abi_for_opt) << "-mfpxx" << "o32";
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return false;
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}
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// -mfp32 and n32/n64 ABIs are incompatible
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if (FPMode != FP64 && FPMode != FPXX && !IsSingleFloat &&
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(ABI == "n32" || ABI == "n64")) {
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Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfpxx" << CPU;
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return false;
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}
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// Mips revision 6 and -mfp32 are incompatible
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if (FPMode != FP64 && FPMode != FPXX && (CPU == "mips32r6" ||
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CPU == "mips64r6")) {
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Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfp32" << CPU;
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return false;
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}
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// Option -mfp64 permitted on Mips32 iff revision 2 or higher is present
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if (FPMode == FP64 && (CPU == "mips1" || CPU == "mips2" ||
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getISARev() < 2) && ABI == "o32") {
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Diags.Report(diag::err_mips_fp64_req) << "-mfp64";
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return false;
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}
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return true;
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}
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