forked from OSchip/llvm-project
140 lines
3.2 KiB
ArmAsm
140 lines
3.2 KiB
ArmAsm
//===-- aeabi_cfcmp.S - EABI cfcmp* implementation ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "../assembly.h"
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#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
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#error big endian support not implemented
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#endif
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#define APSR_Z (1 << 30)
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#define APSR_C (1 << 29)
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// void __aeabi_cfcmpeq(float a, float b) {
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// if (isnan(a) || isnan(b)) {
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// Z = 0; C = 1;
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// } else {
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// __aeabi_cfcmple(a, b);
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// }
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// }
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.syntax unified
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
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push {r0-r3, lr}
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bl __aeabi_cfcmpeq_check_nan
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cmp r0, #1
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#if defined(USE_THUMB_1)
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beq 1f
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// NaN has been ruled out, so __aeabi_cfcmple can't trap
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mov r0, sp
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ldm r0, {r0-r3}
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bl __aeabi_cfcmple
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pop {r0-r3, pc}
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1:
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// Z = 0, C = 1
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movs r0, #0xF
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lsls r0, r0, #31
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pop {r0-r3, pc}
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#else
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pop {r0-r3, lr}
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// NaN has been ruled out, so __aeabi_cfcmple can't trap
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// Use "it ne" + unconditional branch to guarantee a supported relocation if
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// __aeabi_cfcmple is in a different section for some builds.
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IT(ne)
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bne __aeabi_cfcmple
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#if defined(USE_THUMB_2)
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mov ip, #APSR_C
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msr APSR_nzcvq, ip
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#else
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msr APSR_nzcvq, #APSR_C
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#endif
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JMP(lr)
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
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// void __aeabi_cfcmple(float a, float b) {
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// if (__aeabi_fcmplt(a, b)) {
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// Z = 0; C = 0;
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// } else if (__aeabi_fcmpeq(a, b)) {
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// Z = 1; C = 1;
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// } else {
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// Z = 0; C = 1;
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// }
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// }
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.syntax unified
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple)
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// Per the RTABI, this function must preserve r0-r11.
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// Save lr in the same instruction for compactness
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push {r0-r3, lr}
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bl __aeabi_fcmplt
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cmp r0, #1
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#if defined(USE_THUMB_1)
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bne 1f
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// Z = 0, C = 0
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movs r0, #1
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lsls r0, r0, #1
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pop {r0-r3, pc}
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1:
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mov r0, sp
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ldm r0, {r0-r3}
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bl __aeabi_fcmpeq
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cmp r0, #1
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bne 2f
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// Z = 1, C = 1
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movs r0, #2
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lsls r0, r0, #31
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pop {r0-r3, pc}
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2:
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// Z = 0, C = 1
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movs r0, #0xF
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lsls r0, r0, #31
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pop {r0-r3, pc}
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#else
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ITT(eq)
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moveq ip, #0
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beq 1f
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ldm sp, {r0-r3}
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bl __aeabi_fcmpeq
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cmp r0, #1
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ITE(eq)
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moveq ip, #(APSR_C | APSR_Z)
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movne ip, #(APSR_C)
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1:
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msr APSR_nzcvq, ip
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pop {r0-r3}
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POP_PC()
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
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// int __aeabi_cfrcmple(float a, float b) {
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// return __aeabi_cfcmple(b, a);
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// }
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.syntax unified
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.p2align 2
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DEFINE_COMPILERRT_FUNCTION(__aeabi_cfrcmple)
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// Swap r0 and r1
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mov ip, r0
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mov r0, r1
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mov r1, ip
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b __aeabi_cfcmple
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END_COMPILERRT_FUNCTION(__aeabi_cfrcmple)
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NO_EXEC_STACK_DIRECTIVE
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