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173 lines
5.8 KiB
ReStructuredText
173 lines
5.8 KiB
ReStructuredText
=========================
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AMDGPU Instruction Syntax
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=========================
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.. contents::
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:local:
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.. _amdgpu_syn_instructions:
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Instructions
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============
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Syntax
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~~~~~~
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An instruction has the following syntax:
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``<``\ *opcode mnemonic*\ ``> <``\ *operand0*\ ``>, <``\ *operand1*\ ``>,... <``\ *modifier0*\ ``> <``\ *modifier1*\ ``>...``
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:doc:`Operands<AMDGPUOperandSyntax>` are normally comma-separated while
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:doc:`modifiers<AMDGPUModifierSyntax>` are space-separated.
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The order of *operands* and *modifiers* is fixed.
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Most *modifiers* are optional and may be omitted.
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.. _amdgpu_syn_instruction_mnemo:
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Opcode Mnemonic
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~~~~~~~~~~~~~~~
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Opcode mnemonic describes opcode semantics and may include one or more suffices in this order:
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* :ref:`Destination operand type suffix<amdgpu_syn_instruction_type>`.
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* :ref:`Source operand type suffix<amdgpu_syn_instruction_type>`.
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* :ref:`Encoding suffix<amdgpu_syn_instruction_enc>`.
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.. _amdgpu_syn_instruction_type:
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Type and Size Suffices
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~~~~~~~~~~~~~~~~~~~~~~
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Instructions which operate with data have an implied type of *data* operands.
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This data type is specified as a suffix of instruction mnemonic.
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There are instructions which have 2 type suffices:
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the first is the data type of the destination operand,
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the second is the data type of source *data* operand(s).
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Note that data type specified by an instruction does not apply
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to other kinds of operands such as *addresses*, *offsets* and so on.
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The following table enumerates the most frequently used type suffices.
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============================================ ======================= =================
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Type Suffices Packed instruction? Data Type
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============================================ ======================= =================
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_b512, _b256, _b128, _b64, _b32, _b16, _b8 No Bits.
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_u64, _u32, _u16, _u8 No Unsigned integer.
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_i64, _i32, _i16, _i8 No Signed integer.
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_f64, _f32, _f16 No Floating-point.
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_b16, _u16, _i16, _f16 Yes Packed.
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============================================ ======================= =================
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Instructions which have no type suffices are assumed to operate with typeless data.
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The size of data is specified by size suffices:
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================= =================== =====================================
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Size Suffix Implied data type Required register size in dwords
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================= =================== =====================================
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\- b32 1
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x2 b64 2
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x3 b96 3
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x4 b128 4
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x8 b256 8
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x16 b512 16
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x b32 1
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xy b64 2
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xyz b96 3
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xyzw b128 4
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d16_x b16 1
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d16_xy b16x2 2 for GFX8.0, 1 for GFX8.1 and GFX9
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d16_xyz b16x3 3 for GFX8.0, 2 for GFX8.1 and GFX9
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d16_xyzw b16x4 4 for GFX8.0, 2 for GFX8.1 and GFX9
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================= =================== =====================================
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.. WARNING::
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There are exceptions from rules described above.
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Operands which have type different from type specified by the opcode are
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:ref:`tagged<amdgpu_syn_instruction_operand_tags>` in the description.
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Examples of instructions with different types of source and destination operands:
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.. parsed-literal::
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s_bcnt0_i32_b64
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v_cvt_f32_u32
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Examples of instructions with one data type:
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.. parsed-literal::
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v_max3_f32
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v_max3_i16
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Examples of instructions which operate with packed data:
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.. parsed-literal::
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v_pk_add_u16
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v_pk_add_i16
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v_pk_add_f16
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Examples of typeless instructions which operate on b128 data:
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.. parsed-literal::
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buffer_store_dwordx4
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flat_load_dwordx4
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.. _amdgpu_syn_instruction_enc:
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Encoding Suffices
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~~~~~~~~~~~~~~~~~
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Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:
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they may also be encoded in *VOP3*, *DPP* and *SDWA* formats.
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The assembler will automatically use optimal encoding based on instruction operands.
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To force specific encoding, one can add a suffix to the opcode of the instruction:
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=================================================== =================
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Encoding Encoding Suffix
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=================================================== =================
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Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
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*VOP3* (64-bit) encoding _e64
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*DPP* encoding _dpp
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*SDWA* encoding _sdwa
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=================================================== =================
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These suffices are used in this reference to indicate the assumed encoding.
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When no suffix is specified, a native encoding is implied.
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Operands
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========
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Syntax
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~~~~~~
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Syntax of most operands is described :doc:`in this document<AMDGPUOperandSyntax>`.
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For detailed information about operands follow *operand links* in GPU-specific documents:
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* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
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* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
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* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
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* :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`
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Modifiers
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=========
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Syntax
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~~~~~~
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Syntax of modifiers is described :doc:`in this document<AMDGPUModifierSyntax>`.
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Information about modifiers supported for individual instructions may be found in GPU-specific documents:
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* :doc:`GFX7<AMDGPU/AMDGPUAsmGFX7>`
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* :doc:`GFX8<AMDGPU/AMDGPUAsmGFX8>`
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* :doc:`GFX9<AMDGPU/AMDGPUAsmGFX9>`
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* :doc:`GFX10<AMDGPU/AMDGPUAsmGFX10>`
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