forked from OSchip/llvm-project
101 lines
3.5 KiB
LLVM
101 lines
3.5 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}alignbit_shr_pat:
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; GCN-DAG: s_load_dword s[[SHR:[0-9]+]]
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; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
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define amdgpu_kernel void @alignbit_shr_pat(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_v:
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; GCN-DAG: load_dword v[[SHR:[0-9]+]],
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; GCN-DAG: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
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define amdgpu_kernel void @alignbit_shr_pat_v(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
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bb:
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep1 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tid
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%tmp = load i64, i64 addrspace(1)* %gep1, align 8
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%gep2 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i32 %tid
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%amt = load i32, i32 addrspace(1)* %gep2, align 4
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%tmp3 = and i32 %amt, 31
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %gep2, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and30:
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; Negative test, wrong constant
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; GCN: v_lshr_b64
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shr_pat_wrong_and30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 30
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_and63:
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; Negative test, wrong constant
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; GCN: v_lshr_b64
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shr_pat_wrong_and63(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp3 = and i32 %arg2, 63
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = lshr i64 %tmp, %tmp4
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_const30:
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; GCN: load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], 30
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define amdgpu_kernel void @alignbit_shr_pat_const30(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp5 = lshr i64 %tmp, 30
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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; GCN-LABEL: {{^}}alignbit_shr_pat_wrong_const33:
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; Negative test, shift amount more than 31
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; GCN: v_lshrrev_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN-NOT: v_alignbit_b32
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define amdgpu_kernel void @alignbit_shr_pat_wrong_const33(i64 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1) {
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bb:
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%tmp = load i64, i64 addrspace(1)* %arg, align 8
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%tmp5 = lshr i64 %tmp, 33
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%tmp6 = trunc i64 %tmp5 to i32
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store i32 %tmp6, i32 addrspace(1)* %arg1, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone speculatable }
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