forked from OSchip/llvm-project
219 lines
5.7 KiB
LLVM
219 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm -mattr=+v6t2 | FileCheck %s
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%struct.F = type { [3 x i8], i8 }
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@X = common global %struct.F zeroinitializer, align 4 ; <%struct.F*> [#uses=1]
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define void @f1([1 x i32] %f.coerce0) nounwind {
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; CHECK-LABEL: f1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movw r0, :lower16:X
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; CHECK-NEXT: mov r2, #10
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; CHECK-NEXT: movt r0, :upper16:X
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; CHECK-NEXT: ldr r1, [r0]
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; CHECK-NEXT: bfi r1, r2, #22, #4
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; CHECK-NEXT: str r1, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = load i32, i32* bitcast (%struct.F* @X to i32*), align 4 ; <i32> [#uses=1]
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%1 = and i32 %0, -62914561 ; <i32> [#uses=1]
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%2 = or i32 %1, 41943040 ; <i32> [#uses=1]
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store i32 %2, i32* bitcast (%struct.F* @X to i32*), align 4
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ret void
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}
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define i32 @f2(i32 %A, i32 %B) nounwind {
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; CHECK-LABEL: f2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsr r1, r1, #7
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; CHECK-NEXT: bfi r0, r1, #7, #16
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; CHECK-NEXT: bx lr
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entry:
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%and = and i32 %A, -8388481 ; <i32> [#uses=1]
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%and2 = and i32 %B, 8388480 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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define i32 @f3(i32 %A, i32 %B) nounwind {
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; CHECK-LABEL: f3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsr r0, r0, #7
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; CHECK-NEXT: bfi r1, r0, #7, #16
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%and = and i32 %A, 8388480 ; <i32> [#uses=1]
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%and2 = and i32 %B, -8388481 ; <i32> [#uses=1]
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%or = or i32 %and2, %and ; <i32> [#uses=1]
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ret i32 %or
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}
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; rdar://8752056
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define i32 @f4(i32 %a) nounwind {
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; CHECK-LABEL: f4:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: movw r1, #3137
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; CHECK-NEXT: bfi r1, r0, #15, #5
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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%1 = shl i32 %a, 15
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%ins7 = and i32 %1, 1015808
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%ins12 = or i32 %ins7, 3137
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ret i32 %ins12
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}
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; rdar://8458663
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define i32 @f5(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: f5:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bfi r0, r1, #20, #4
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; CHECK-NEXT: bx lr
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entry:
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%0 = and i32 %a, -15728641
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%1 = shl i32 %b, 20
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%2 = and i32 %1, 15728640
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%3 = or i32 %2, %0
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ret i32 %3
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}
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; rdar://9609030
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define i32 @f6(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: f6:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bfi r0, r1, #8, #9
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; CHECK-NEXT: bx lr
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entry:
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%and = and i32 %a, -130817
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%and2 = shl i32 %b, 8
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%shl = and i32 %and2, 130816
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @f7(i32 %x, i32 %y) {
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; CHECK-LABEL: f7:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r2, r0, #2
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; CHECK-NEXT: bic r0, r1, #255
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; CHECK-NEXT: bfi r0, r2, #4, #1
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 16
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%cmp = icmp ne i32 %and, 0
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%sel = select i1 %cmp, i32 %or, i32 %y2
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ret i32 %sel
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}
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define i32 @f8(i32 %x, i32 %y) {
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; CHECK-LABEL: f8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r2, r0, #2
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; CHECK-NEXT: bic r0, r1, #255
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; CHECK-NEXT: bfi r0, r2, #4, #1
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; CHECK-NEXT: bfi r0, r2, #5, #1
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 48
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%cmp = icmp ne i32 %and, 0
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%sel = select i1 %cmp, i32 %or, i32 %y2
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ret i32 %sel
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}
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define i32 @f9(i32 %x, i32 %y) {
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; CHECK-LABEL: f9:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: bic r1, r1, #255
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; CHECK-NEXT: tst r0, #4
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; CHECK-NEXT: orreq r1, r1, #48
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 48
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%cmp = icmp ne i32 %and, 0
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%sel = select i1 %cmp, i32 %y2, i32 %or
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ret i32 %sel
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}
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define i32 @f10(i32 %x, i32 %y) {
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; CHECK-LABEL: f10:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r2, r0, #1
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; CHECK-NEXT: bic r0, r1, #255
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; CHECK-NEXT: bfi r0, r2, #4, #2
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 32
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%cmp = icmp ne i32 %and, 0
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%sel = select i1 %cmp, i32 %or, i32 %y2
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%aand = and i32 %x, 2
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%aor = or i32 %sel, 16
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%acmp = icmp ne i32 %aand, 0
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%asel = select i1 %acmp, i32 %aor, i32 %sel
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ret i32 %asel
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}
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define i32 @f11(i32 %x, i32 %y) {
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; CHECK-LABEL: f11:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r2, r0, #1
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; CHECK-NEXT: bic r0, r1, #255
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; CHECK-NEXT: bfi r0, r2, #4, #3
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 32
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%cmp = icmp ne i32 %and, 0
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%sel = select i1 %cmp, i32 %or, i32 %y2
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%aand = and i32 %x, 2
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%aor = or i32 %sel, 16
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%acmp = icmp ne i32 %aand, 0
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%asel = select i1 %acmp, i32 %aor, i32 %sel
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%band = and i32 %x, 8
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%bor = or i32 %asel, 64
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%bcmp = icmp ne i32 %band, 0
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%bsel = select i1 %bcmp, i32 %bor, i32 %asel
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ret i32 %bsel
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}
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define i32 @f12(i32 %x, i32 %y) {
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; CHECK-LABEL: f12:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: lsr r2, r0, #2
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; CHECK-NEXT: bic r0, r1, #255
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; CHECK-NEXT: bfi r0, r2, #4, #1
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 16
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%cmp = icmp eq i32 %and, 0
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%sel = select i1 %cmp, i32 %y2, i32 %or
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ret i32 %sel
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}
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define i32 @f13(i32 %x, i32 %y) {
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; CHECK-LABEL: f13:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: and r2, r0, #4
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; CHECK-NEXT: bic r0, r1, #255
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; CHECK-NEXT: cmp r2, #42
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; CHECK-NEXT: orrne r0, r0, #16
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; CHECK-NEXT: bx lr
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 16
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%cmp = icmp eq i32 %and, 42 ; Not comparing against zero!
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%sel = select i1 %cmp, i32 %y2, i32 %or
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ret i32 %sel
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}
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