forked from OSchip/llvm-project
30 lines
1.2 KiB
LLVM
30 lines
1.2 KiB
LLVM
; RUN: llc -O0 -march=hexagon < %s | FileCheck %s
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; CHECK: [[REG0:(r[0-9]+)]] = add(r{{[0-9]+}},mpyi([[REG0]],r{{[0-9]+}})
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; CHECK: [[REG0:(r[0-9]+)]] = add(r{{[0-9]+}},mpyi([[REG0]],r{{[0-9]+}})
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target triple = "hexagon"
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@g0 = private unnamed_addr constant [50 x i8] c"%x : Q6_R_add_mpyi_RRR(INT_MIN,INT_MIN,INT_MIN)\0A\00", align 1
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@g1 = private unnamed_addr constant [45 x i8] c"%x : Q6_R_add_mpyi_RRR(-1,INT_MIN,INT_MIN)\0A\00", align 1
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; Function Attrs: nounwind
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declare i32 @f0(i8* nocapture readonly, ...) #0
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; Function Attrs: nounwind
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define i32 @f1() #0 {
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b0:
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%v0 = tail call i32 @llvm.hexagon.M4.mpyrr.addr(i32 -2147483648, i32 -2147483648, i32 -2147483648)
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%v1 = tail call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @g0, i32 0, i32 0), i32 %v0) #2
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%v2 = tail call i32 @llvm.hexagon.M4.mpyrr.addr(i32 -1, i32 -2147483648, i32 -2147483648)
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%v3 = tail call i32 (i8*, ...) @f0(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @g1, i32 0, i32 0), i32 %v2) #2
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M4.mpyrr.addr(i32, i32, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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