forked from OSchip/llvm-project
94 lines
3.3 KiB
LLVM
94 lines
3.3 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Make sure that the loop in the end has only one basic block.
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; CHECK-LABEL: fred
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; CHECK: %b2
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; Rely on the comments, make sure the one for the loop header is present.
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; CHECK: %loop
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; CHECK: %should_merge
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; CHECK: %exit
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target triple = "hexagon"
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define i32 @fred(i32 %a0, i64* nocapture readonly %a1) #0 {
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b2:
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%v3 = bitcast i64* %a1 to i32*
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%v4 = getelementptr inbounds i32, i32* %v3, i32 1
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%v5 = zext i32 %a0 to i64
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br label %loop
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loop: ; preds = %should_merge, %b2
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%v7 = phi i32 [ 0, %b2 ], [ %v49, %should_merge ]
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%v8 = phi i32 [ 0, %b2 ], [ %v42, %should_merge ]
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%v9 = phi i32* [ %v4, %b2 ], [ %v53, %should_merge ]
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%v10 = phi i32 [ 0, %b2 ], [ %v30, %should_merge ]
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%v11 = phi i32* [ %v3, %b2 ], [ %v51, %should_merge ]
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%v12 = phi i32 [ 0, %b2 ], [ %v23, %should_merge ]
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%v13 = phi i32 [ 2, %b2 ], [ %v54, %should_merge ]
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%v14 = load i32, i32* %v11, align 4, !tbaa !0
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%v15 = load i32, i32* %v9, align 4, !tbaa !0
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%v16 = icmp ult i32 %v13, 30
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%v17 = zext i32 %v12 to i64
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%v18 = shl nuw i64 %v17, 32
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%v19 = zext i32 %v14 to i64
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%v20 = or i64 %v18, %v19
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%v21 = tail call i64 @llvm.hexagon.A2.addp(i64 %v20, i64 %v5)
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%v22 = lshr i64 %v21, 32
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%v23 = trunc i64 %v22 to i32
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%v24 = zext i32 %v10 to i64
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%v25 = shl nuw i64 %v24, 32
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%v26 = zext i32 %v15 to i64
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%v27 = or i64 %v25, %v26
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%v28 = tail call i64 @llvm.hexagon.A2.addp(i64 %v27, i64 %v5)
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%v29 = lshr i64 %v28, 32
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%v30 = trunc i64 %v29 to i32
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%v31 = getelementptr inbounds i32, i32* %v3, i32 %v13
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%v32 = load i32, i32* %v31, align 4, !tbaa !0
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%v33 = or i32 %v13, 1
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%v34 = getelementptr inbounds i32, i32* %v3, i32 %v33
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%v35 = load i32, i32* %v34, align 4, !tbaa !0
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%v36 = zext i32 %v8 to i64
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%v37 = shl nuw i64 %v36, 32
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%v38 = zext i32 %v32 to i64
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%v39 = or i64 %v37, %v38
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%v40 = tail call i64 @llvm.hexagon.A2.subp(i64 %v39, i64 %v5)
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%v41 = lshr i64 %v40, 32
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%v42 = trunc i64 %v41 to i32
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%v43 = zext i32 %v7 to i64
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%v44 = shl nuw i64 %v43, 32
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%v45 = zext i32 %v35 to i64
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%v46 = or i64 %v44, %v45
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%v47 = tail call i64 @llvm.hexagon.A2.subp(i64 %v46, i64 %v5)
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%v48 = lshr i64 %v47, 32
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%v49 = trunc i64 %v48 to i32
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br i1 %v16, label %should_merge, label %exit
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should_merge: ; preds = %loop
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%v50 = add nuw nsw i32 %v13, 2
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%v51 = getelementptr inbounds i32, i32* %v3, i32 %v50
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%v52 = add nuw nsw i32 %v13, 3
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%v53 = getelementptr inbounds i32, i32* %v3, i32 %v52
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%v54 = add nuw nsw i32 %v13, 4
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br label %loop
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exit: ; preds = %loop
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%v57 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v42, i32 %v23)
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%v58 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v49, i32 %v30)
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%v59 = tail call i64 @llvm.hexagon.A2.addp(i64 %v57, i64 %v58)
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%v60 = lshr i64 %v59, 32
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%v61 = trunc i64 %v60 to i32
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ret i32 %v61
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}
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declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
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declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
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attributes #1 = { nounwind readnone }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"long", !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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