forked from OSchip/llvm-project
71 lines
1.9 KiB
LLVM
71 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Test that we generate a hardware loop for long long counters.
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; Tests signed/unsigned GT, EQ, and NEQ cases.
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; signed GT case
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; CHECK-LABEL: f0:
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; CHECK: loop0
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define i32 @f0(i32* nocapture %a0) #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
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%v1 = phi i64 [ 0, %b0 ], [ %v6, %b1 ]
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%v2 = trunc i64 %v1 to i32
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%v3 = getelementptr inbounds i32, i32* %a0, i32 %v2
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%v4 = load i32, i32* %v3, align 4
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%v5 = add nsw i32 %v4, %v0
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%v6 = add nsw i64 %v1, 1
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%v7 = icmp slt i64 %v6, 8
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br i1 %v7, label %b1, label %b2
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b2: ; preds = %b1
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ret i32 %v5
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}
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; unsigned signed GT case
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; CHECK-LABEL: f1:
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; CHECK: loop0
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define i32 @f1(i32* nocapture %a0) #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
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%v1 = phi i64 [ 0, %b0 ], [ %v6, %b1 ]
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%v2 = trunc i64 %v1 to i32
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%v3 = getelementptr inbounds i32, i32* %a0, i32 %v2
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%v4 = load i32, i32* %v3, align 4
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%v5 = add nsw i32 %v4, %v0
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%v6 = add i64 %v1, 1
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%v7 = icmp ult i64 %v6, 8
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br i1 %v7, label %b1, label %b2
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b2: ; preds = %b1
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ret i32 %v5
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}
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; EQ case
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; CHECK-LABEL: f2:
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; CHECK: loop0
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define i32 @f2(i32* nocapture %a0) #0 {
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b0:
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br label %b1
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b1: ; preds = %b1, %b0
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%v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]
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%v1 = phi i64 [ 0, %b0 ], [ %v6, %b1 ]
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%v2 = trunc i64 %v1 to i32
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%v3 = getelementptr inbounds i32, i32* %a0, i32 %v2
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%v4 = load i32, i32* %v3, align 4
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%v5 = add nsw i32 %v4, %v0
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%v6 = add nsw i64 %v1, 1
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%v7 = icmp eq i64 %v6, 8
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br i1 %v7, label %b2, label %b1
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b2: ; preds = %b1
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ret i32 %v5
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}
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attributes #0 = { nounwind readonly "target-cpu"="hexagonv55" }
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