forked from OSchip/llvm-project
33 lines
1.4 KiB
LLVM
33 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we generate a hardware loop instruction.
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; CHECK: endloop0
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@A = common global [400 x i8] zeroinitializer, align 8
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@B = common global [400 x i8] zeroinitializer, align 8
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@C = common global [400 x i8] zeroinitializer, align 8
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define void @run() nounwind {
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entry:
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br label %polly.loop_body
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polly.loop_after: ; preds = %polly.loop_body
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ret void
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polly.loop_body: ; preds = %entry, %polly.loop_body
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%polly.loopiv16 = phi i32 [ 0, %entry ], [ %polly.next_loopiv, %polly.loop_body ]
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%polly.next_loopiv = add i32 %polly.loopiv16, 4
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%p_vector_iv14 = or i32 %polly.loopiv16, 1
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%p_vector_iv3 = add i32 %p_vector_iv14, 1
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%p_vector_iv415 = or i32 %polly.loopiv16, 3
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%p_arrayidx = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %polly.loopiv16
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%p_arrayidx5 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv14
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%p_arrayidx6 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv3
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%p_arrayidx7 = getelementptr [400 x i8], [400 x i8]* @A, i32 0, i32 %p_vector_iv415
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store i8 123, i8* %p_arrayidx, align 1
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store i8 123, i8* %p_arrayidx5, align 1
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store i8 123, i8* %p_arrayidx6, align 1
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store i8 123, i8* %p_arrayidx7, align 1
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%0 = icmp slt i32 %polly.next_loopiv, 400
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br i1 %0, label %polly.loop_body, label %polly.loop_after
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}
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