forked from OSchip/llvm-project
42 lines
1.3 KiB
LLVM
42 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -enable-pipeliner < %s
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; REQUIRES: asserts
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; Check that a dead REG_SEQUENCE doesn't ICE.
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; Function Attrs: nounwind
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define void @f0(i32* nocapture %a0, i32 %a1) #0 {
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b0:
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%v0 = mul nsw i32 %a1, 4
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%v1 = icmp sgt i32 %v0, 0
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br i1 %v1, label %b1, label %b2
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b1: ; preds = %b1, %b0
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%v2 = phi i32 [ %v11, %b1 ], [ 0, %b0 ]
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%v3 = load i32, i32* null, align 4
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%v4 = zext i32 %v3 to i64
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%v5 = getelementptr inbounds i32, i32* %a0, i32 0
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%v6 = load i32, i32* %v5, align 4
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%v7 = zext i32 %v6 to i64
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%v8 = shl nuw i64 %v7, 32
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%v9 = or i64 %v8, %v4
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%v10 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 0, i64 %v9, i64 %v9)
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%v11 = add nsw i32 %v2, 4
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%v12 = icmp slt i32 %v11, %v0
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br i1 %v12, label %b1, label %b2
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b2: ; preds = %b1, %b0
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%v13 = phi i64 [ 0, %b0 ], [ %v10, %b1 ]
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%v14 = tail call i64 @llvm.hexagon.S2.asr.r.vw(i64 %v13, i32 6)
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store i64 %v14, i64* null, align 8
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.asr.r.vw(i64, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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