forked from OSchip/llvm-project
				
			
		
			
				
	
	
		
			55 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			LLVM
		
	
	
	
			
		
		
	
	
			55 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			LLVM
		
	
	
	
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 -pipeliner-experimental-cg=true < %s | FileCheck %s
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; Test epilogue generation when reading loop-carried dependency from a previous
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; stage. The first epilogue should read value from iteration N-1 of the kernel.
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; CHECK: loop0
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; CHECK: r{{[0-9]+}} = add([[REG0:r([0-9]+)]],#8)
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; CHECK: [[REG0]] = [[REG1:r([0-9]+)]]
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; CHECK: endloop0
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; CHECK: = add([[REG1]],#8)
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; Function Attrs: nounwind
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define i32* @f0(i16* nocapture readonly %a0, i32 %a1) #0 {
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b0:
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  %v0 = alloca [129 x i32], align 8
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  br i1 undef, label %b1, label %b3
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b1:                                               ; preds = %b0
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  br label %b2
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b2:                                               ; preds = %b2, %b1
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  %v1 = phi i16* [ %a0, %b1 ], [ %v2, %b2 ]
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  %v2 = phi i16* [ undef, %b1 ], [ %v15, %b2 ]
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  %v3 = phi i32* [ null, %b1 ], [ %v4, %b2 ]
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  %v4 = phi i32* [ null, %b1 ], [ %v14, %b2 ]
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  %v5 = phi i32 [ 0, %b1 ], [ %v13, %b2 ]
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  %v6 = phi i16* [ undef, %b1 ], [ %v12, %b2 ]
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  %v7 = load i16, i16* %v2, align 2
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  %v8 = sext i16 %v7 to i32
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  %v9 = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %v8, i32 %v8) #2
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  %v10 = load i16, i16* %v6, align 2
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  %v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %v9, i32 undef, i32 undef) #2
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  store i32 %v11, i32* %v4, align 4
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  %v12 = getelementptr inbounds i16, i16* %v6, i32 -1
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  %v13 = add i32 %v5, 1
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  %v14 = getelementptr inbounds i32, i32* %v3, i32 2
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  %v15 = getelementptr inbounds i16, i16* %v1, i32 2
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  %v16 = icmp slt i32 %v13, %a1
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  br i1 %v16, label %b2, label %b3
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b3:                                               ; preds = %b2, %b0
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  %out = phi i32* [ null, %b0 ], [ %v14, %b2 ]
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  ret i32* %out
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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