forked from OSchip/llvm-project
60 lines
1.9 KiB
LLVM
60 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon < %s
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; REQUIRES: asserts
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; Function Attrs: nounwind
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define void @f0(i32 %a0) #0 {
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b0:
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%v0 = ashr i32 %a0, 1
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br label %b1
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b1: ; preds = %b1, %b0
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%v1 = phi i32 [ %v17, %b1 ], [ undef, %b0 ]
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%v2 = phi i32 [ %v19, %b1 ], [ 0, %b0 ]
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%v3 = phi i32 [ %v4, %b1 ], [ undef, %b0 ]
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%v4 = phi i32 [ %v14, %b1 ], [ undef, %b0 ]
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%v5 = phi i32 [ %v18, %b1 ], [ undef, %b0 ]
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%v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v1, i32 undef)
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%v7 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v3, i32 %v3)
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%v8 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v6, i64 undef, i32 2)
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%v9 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v7, i64 %v8)
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%v10 = inttoptr i32 %v5 to i16*
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%v11 = load i16, i16* %v10, align 2
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%v12 = sext i16 %v11 to i32
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%v13 = add nsw i32 %v5, -8
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%v14 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v12, i32 %v1)
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%v15 = inttoptr i32 %v13 to i16*
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%v16 = load i16, i16* %v15, align 2
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%v17 = sext i16 %v16 to i32
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%v18 = add nsw i32 %v5, -16
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%v19 = add nsw i32 %v2, 1
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%v20 = icmp eq i32 %v19, %v0
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br i1 %v20, label %b2, label %b1
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b2: ; preds = %b1
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%v21 = phi i64 [ %v9, %b1 ]
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%v22 = trunc i64 %v21 to i32
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%v23 = bitcast i8* undef to i32*
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store i32 %v22, i32* %v23, align 4
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call void @llvm.trap()
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #1
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; Function Attrs: noreturn nounwind
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declare void @llvm.trap() #2
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attributes #0 = { nounwind "target-cpu"="hexagonv60" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { noreturn nounwind }
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