forked from OSchip/llvm-project
227 lines
6.1 KiB
LLVM
227 lines
6.1 KiB
LLVM
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -verify-machineinstrs \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck %s
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@a_qp = common global fp128 0xL00000000000000000000000000000000, align 16
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@b_qp = common global fp128 0xL00000000000000000000000000000000, align 16
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; Function Attrs: noinline nounwind optnone
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define signext i32 @greater_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ogt fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: greater_qp
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; CHECK: xscmpuqp
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; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, gt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @less_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp olt fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: less_qp
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; CHECK: xscmpuqp
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; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, lt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @greater_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oge fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: greater_eq_qp
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; CHECK: xscmpuqp
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; CHECK: cror 4*cr[[REG:[0-9]+]]+lt, un, lt
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @less_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ole fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: less_eq_qp
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; CHECK: xscmpuqp
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; CHECK: cror 4*cr[[REG:[0-9]+]]+lt, un, gt
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @equal_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oeq fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: equal_qp
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; CHECK: xscmpuqp
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; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, eq
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_greater_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ogt fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_greater_qp
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; CHECK: xscmpuqp
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, gt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_less_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp olt fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_less_qp
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; CHECK: xscmpuqp
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, lt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_greater_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oge fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_greater_eq_qp
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; CHECK: xscmpuqp
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; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, lt, un
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_less_eq_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ole fp128 %0, %1
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%lnot = xor i1 %cmp, true
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%lnot.ext = zext i1 %lnot to i32
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ret i32 %lnot.ext
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; CHECK-LABEL: not_less_eq_qp
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; CHECK: xscmpuqp
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; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, gt, un
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, 4*cr[[REG]]+lt
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define signext i32 @not_equal_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp une fp128 %0, %1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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; CHECK-LABEL: not_equal_qp
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; CHECK: xscmpuqp
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; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, eq
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; CHECK: blr
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}
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; Function Attrs: norecurse nounwind readonly
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define fp128 @greater_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ogt fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: greater_sel_qp
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; CHECK: xscmpuqp cr[[REG:[0-9]+]]
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; CHECK: bgtlr cr[[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define fp128 @less_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp olt fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: less_sel_qp
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; CHECK: xscmpuqp cr[[REG:[0-9]+]]
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; CHECK: bltlr cr[[REG]]
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define fp128 @greater_eq_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oge fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: greater_eq_sel_qp
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; CHECK: xscmpuqp
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; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, un, lt
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; CHECK: bclr {{[0-9]+}}, 4*cr[[REG]]+lt, 0
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define fp128 @less_eq_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp ole fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: less_eq_sel_qp
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; CHECK: xscmpuqp
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; CHECK: crnor 4*cr[[REG:[0-9]+]]+lt, un, gt
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; CHECK: bclr {{[0-9]+}}, 4*cr[[REG]]+lt, 0
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; CHECK: blr
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}
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; Function Attrs: noinline nounwind optnone
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define fp128 @equal_sel_qp() {
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entry:
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%0 = load fp128, fp128* @a_qp, align 16
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%1 = load fp128, fp128* @b_qp, align 16
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%cmp = fcmp oeq fp128 %0, %1
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%cond = select i1 %cmp, fp128 %0, fp128 %1
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ret fp128 %cond
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; CHECK-LABEL: equal_sel_qp
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; CHECK: xscmpuqp cr[[REG:[0-9]+]]
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; CHECK: beqlr cr[[REG]]
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; CHECK: blr
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}
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