forked from OSchip/llvm-project
214 lines
5.9 KiB
LLVM
214 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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declare i32 @llvm.fshl.i32(i32, i32, i32)
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare i8 @llvm.fshr.i8(i8, i8, i8)
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declare i16 @llvm.fshr.i16(i16, i16, i16)
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declare i32 @llvm.fshr.i32(i32, i32, i32)
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; When first 2 operands match, it's a rotate.
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define i8 @rotl_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotl_i8_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31
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; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i64 @rotl_i64_const_shift(i64 %x) {
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; CHECK-LABEL: rotl_i64_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rotldi 3, 3, 3
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; CHECK-NEXT: blr
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
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ret i64 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotl_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotl_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: neg 5, 4
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; CHECK-NEXT: clrlwi 6, 3, 16
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; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
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; CHECK-NEXT: clrlwi 5, 5, 28
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; CHECK-NEXT: slw 3, 3, 4
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; CHECK-NEXT: srw 4, 6, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: blr
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%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotl_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotl_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotl_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotl_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rldcl 3, 3, 4, 0
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; CHECK-NEXT: blr
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; CHECK-LABEL: rotl_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vrlw 2, 2, 3
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) {
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; CHECK-LABEL: rotl_v4i32_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, 3
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; CHECK-NEXT: vrlw 2, 2, 3
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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; Repeat everything for funnel shift right.
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define i8 @rotr_i8_const_shift(i8 %x) {
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; CHECK-LABEL: rotr_i8_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31
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; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26
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; CHECK-NEXT: mr 3, 4
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; CHECK-NEXT: blr
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%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
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ret i8 %f
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}
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define i32 @rotr_i32_const_shift(i32 %x) {
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; CHECK-LABEL: rotr_i32_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
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ret i32 %f
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}
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotr_i16(i16 %x, i16 %z) {
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; CHECK-LABEL: rotr_i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: neg 5, 4
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; CHECK-NEXT: clrlwi 6, 3, 16
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; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31
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; CHECK-NEXT: clrlwi 5, 5, 28
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; CHECK-NEXT: srw 4, 6, 4
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; CHECK-NEXT: slw 3, 3, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: blr
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%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
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ret i16 %f
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}
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define i32 @rotr_i32(i32 %x, i32 %z) {
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; CHECK-LABEL: rotr_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: neg 4, 4
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; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
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ret i32 %f
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}
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define i64 @rotr_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotr_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: neg 4, 4
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; CHECK-NEXT: rldcl 3, 3, 4, 0
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; CHECK-NEXT: blr
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
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ret i64 %f
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}
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; Vector rotate.
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define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
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; CHECK-LABEL: rotr_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vrlw 2, 2, 3
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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ret <4 x i32> %f
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}
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
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; CHECK-LABEL: rotr_v4i32_const_shift:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vspltisw 3, -16
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; CHECK-NEXT: vspltisw 4, 13
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; CHECK-NEXT: vsubuwm 3, 4, 3
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; CHECK-NEXT: vrlw 2, 2, 3
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
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ret <4 x i32> %f
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}
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define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
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}
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define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
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; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blr
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%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
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ret i32 %f
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}
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define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
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; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
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; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
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; CHECK: # %bb.0:
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; CHECK-NEXT: blr
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
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ret <4 x i32> %f
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}
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