forked from OSchip/llvm-project
46 lines
1.1 KiB
LLVM
46 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
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; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
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@a = common global i32 0
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define i32 @test_load() {
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entry:
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%0 = load i32, i32* @a
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ret i32 %0
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}
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; SMALL-LABEL: .test_load:{{$}}
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; SMALL: lwz [[REG1:[0-9]+]], LC0(2)
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; SMALL: lwz [[REG2:[0-9]+]], 0([[REG1]])
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; SMALL: blr
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; LARGE-LABEL: .test_load:{{$}}
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; LARGE: addis [[REG1:[0-9]+]], LC0@u(2)
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; LARGE: lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
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; LARGE: lwz [[REG3:[0-9]+]], 0([[REG2]])
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; LARGE: blr
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@b = common global i32 0
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define void @test_store(i32 %0) {
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store i32 %0, i32* @b
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ret void
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}
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; SMALL-LABEL: .test_store:{{$}}
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; SMALL: lwz [[REG1:[0-9]+]], LC1(2)
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; SMALL: stw [[REG2:[0-9]+]], 0([[REG1]])
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; SMALL: blr
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; LARGE-LABEL: .test_store:{{$}}
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; LARGE: addis [[REG1:[0-9]+]], LC1@u(2)
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; LARGE: lwz [[REG2:[0-9]+]], LC1@l([[REG1]])
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; LARGE: stw [[REG3:[0-9]+]], 0([[REG2]])
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; LARGE: blr
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; CHECK: .tc a[TC],a
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; CHECK: .tc b[TC],b
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