forked from OSchip/llvm-project
41 lines
1.3 KiB
LLVM
41 lines
1.3 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; Check the vabsd* instructions that were added in PowerISA V3.0
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; Function Attrs: nounwind readnone
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declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)
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define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {
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entry:
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%res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %res
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; CHECK-LABEL: @test_byte
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; CHECK: vabsdub 2, 2, 3
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; CHECK: blr
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}
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define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
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entry:
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%res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)
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ret <8 x i16> %res
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; CHECK-LABEL: @test_half
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; CHECK: vabsduh 2, 2, 3
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; CHECK: blr
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}
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define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {
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entry:
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%res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)
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ret <4 x i32> %res
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; CHECK-LABEL: @test_word
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; CHECK: vabsduw 2, 2, 3
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; CHECK: blr
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}
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