forked from OSchip/llvm-project
67 lines
1.6 KiB
LLVM
67 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -filetype=obj < %s \
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; RUN: -o /dev/null 2>&1
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
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define void @relax_bcc(i1 %a) nounwind {
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; CHECK-LABEL: relax_bcc:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: bnez a0, .LBB0_1
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; CHECK-NEXT: j .LBB0_2
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; CHECK-NEXT: .LBB0_1: # %iftrue
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; CHECK-NEXT: #APP
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; CHECK-NEXT: .space 4096
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: .LBB0_2: # %tail
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; CHECK-NEXT: ret
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br i1 %a, label %iftrue, label %tail
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iftrue:
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call void asm sideeffect ".space 4096", ""()
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br label %tail
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tail:
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ret void
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}
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; TODO: Extend simm12's MCOperandPredicate so the jalr zero is printed as a jr.
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define i32 @relax_jal(i1 %a) nounwind {
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; CHECK-LABEL: relax_jal:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andi a0, a0, 1
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; CHECK-NEXT: bnez a0, .LBB1_1
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; CHECK-NEXT: # %bb.3:
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; CHECK-NEXT: lui a0, %hi(.LBB1_2)
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; CHECK-NEXT: jalr zero, %lo(.LBB1_2)(a0)
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; CHECK-NEXT: .LBB1_1: # %iftrue
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: #APP
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; CHECK-NEXT: .space 1048576
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_2: # %jmp
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; CHECK-NEXT: #APP
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: addi a0, zero, 1
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; CHECK-NEXT: ret
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br i1 %a, label %iftrue, label %jmp
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jmp:
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call void asm sideeffect "", ""()
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br label %tail
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iftrue:
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call void asm sideeffect "", ""()
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br label %space
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space:
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call void asm sideeffect ".space 1048576", ""()
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br label %tail
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tail:
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ret i32 1
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}
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