forked from OSchip/llvm-project
66 lines
2.3 KiB
LLVM
66 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-MVE
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; RUN: llc --verify-machineinstrs -mtriple=thumbv8.1m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-NOMVE
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define void @test1(i32* %p0, i32 *%p1, i32 *%p2, i32 *%pDst) {
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; CHECK-MVE-LABEL: test1:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: ldr r1, [r1]
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; CHECK-MVE-NEXT: ldr r2, [r2]
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; CHECK-MVE-NEXT: ldr r0, [r0]
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; CHECK-MVE-NEXT: smull r2, r1, r2, r1
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; CHECK-MVE-NEXT: lsrl r2, r1, #31
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; CHECK-MVE-NEXT: bic r1, r2, #1
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; CHECK-MVE-NEXT: add r0, r1
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; CHECK-MVE-NEXT: str r0, [r3]
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-NOMVE-LABEL: test1:
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; CHECK-NOMVE: @ %bb.0: @ %entry
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; CHECK-NOMVE-NEXT: ldr r1, [r1]
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; CHECK-NOMVE-NEXT: ldr r2, [r2]
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; CHECK-NOMVE-NEXT: ldr r0, [r0]
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; CHECK-NOMVE-NEXT: smmul r1, r2, r1
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; CHECK-NOMVE-NEXT: add.w r0, r0, r1, lsl #1
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; CHECK-NOMVE-NEXT: str r0, [r3]
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; CHECK-NOMVE-NEXT: bx lr
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entry:
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%l3 = load i32, i32* %p0, align 4
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%l4 = load i32, i32* %p1, align 4
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%conv5.us = sext i32 %l4 to i64
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%l5 = load i32, i32* %p2, align 4
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%conv6.us = sext i32 %l5 to i64
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%mul.us = mul nsw i64 %conv6.us, %conv5.us
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%l6 = lshr i64 %mul.us, 31
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%l7 = trunc i64 %l6 to i32
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%shl.us = and i32 %l7, -2
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%add.us = add nsw i32 %shl.us, %l3
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store i32 %add.us, i32* %pDst, align 4
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ret void
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}
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define void @test2(i32* %p0, i32 *%p1, i32 *%p2, i32 *%pDst) {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldr r1, [r1]
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; CHECK-NEXT: ldr r2, [r2]
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: smmul r1, r2, r1
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; CHECK-NEXT: add.w r0, r0, r1, lsl #1
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; CHECK-NEXT: str r0, [r3]
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; CHECK-NEXT: bx lr
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entry:
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%l3 = load i32, i32* %p0, align 4
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%l4 = load i32, i32* %p1, align 4
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%conv5.us = sext i32 %l4 to i64
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%l5 = load i32, i32* %p2, align 4
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%conv6.us = sext i32 %l5 to i64
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%mul.us = mul nsw i64 %conv6.us, %conv5.us
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%l6 = lshr i64 %mul.us, 32
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%shl74.us = shl nuw nsw i64 %l6, 1
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%shl.us = trunc i64 %shl74.us to i32
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%add.us = add nsw i32 %l3, %shl.us
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store i32 %add.us, i32* %pDst, align 4
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ret void
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}
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