forked from OSchip/llvm-project
dd4d093762
Summary: This patch adds assembly-level support for a new Arm M-profile architecture extension, Custom Datapath Extension (CDE). A brief description of the extension is available at https://developer.arm.com/architectures/instruction-sets/custom-instructions The latest specification for CDE is currently a beta release and is available at https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf CDE allows chip vendors to add custom CPU instructions. The CDE instructions re-use the same encoding space as existing coprocessor instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range cp0-cp7 can be configured as either general purpose (GCP) or custom datapath (CDEv1). This configuration is defined by the CPU vendor and is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7. The semantics of CDE instructions are implementation-defined, but the instructions are guaranteed to be pure (that is, they are stateless, they do not access memory or any registers except their explicit inputs/outputs). CDE requires the CPU to support at least Armv8.0-M mainline architecture. CDE includes 3 sets of instructions: * Instructions that operate on general purpose registers and NZCV flags * Instructions that operate on the S or D register file (require either FP or MVE extension) * Instructions that operate on the Q register file, require MVE The user-facing names that can be specified on the command line are the same as the 8 subtarget feature names. For example: $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 tells the compiler that the coprocessors 0 and 3 are configured as CDEv1 and the remaining coprocessors are configured as GCP (which is the default). Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74044 |
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| .. | ||
| addrmode2-reencoding.txt | ||
| arm-LDREXD-reencoding.txt | ||
| arm-STREXD-reencoding.txt | ||
| arm-tests.txt | ||
| arm-thumb-trustzone.txt | ||
| arm-trustzone.txt | ||
| arm-vmrs_vmsr.txt | ||
| armv8.1a.txt | ||
| armv8.2a-dotprod-a32.s | ||
| armv8.2a-dotprod-t32.s | ||
| armv8.3a-js-arm.txt | ||
| armv8.3a-js-thumb.txt | ||
| armv8.4a-trace-a32.txt | ||
| armv8.4a-trace-t32.txt | ||
| armv8.5a-sb-thumb.txt | ||
| armv8.5a-sb.txt | ||
| armv8a-fpmul-a32.txt | ||
| armv8a-fpmul-t32.txt | ||
| basic-arm-instructions-v8.txt | ||
| basic-arm-instructions.txt | ||
| cde-fp-vec.txt | ||
| cde-integer.txt | ||
| cde-vec-pred.txt | ||
| clrm.txt | ||
| coprocessors-arm.txt | ||
| coprocessors-thumb.txt | ||
| crc32-thumb.txt | ||
| crc32.txt | ||
| csdb-arm.txt | ||
| csdb-thumb.txt | ||
| d16.txt | ||
| dfb-arm.txt | ||
| dfb-thumb.txt | ||
| fp-armv8.txt | ||
| fp-encoding.txt | ||
| fullfp16-arm-neg.txt | ||
| fullfp16-arm-nopred.txt | ||
| fullfp16-arm.txt | ||
| fullfp16-neon-arm-neg.txt | ||
| fullfp16-neon-arm.txt | ||
| fullfp16-neon-thumb-neg.txt | ||
| fullfp16-neon-thumb.txt | ||
| fullfp16-thumb-neg.txt | ||
| fullfp16-thumb-nopred.txt | ||
| fullfp16-thumb.txt | ||
| hex-immediates.txt | ||
| invalid-FSTMX-arm.txt | ||
| invalid-IT-CC15.txt | ||
| invalid-armv7.txt | ||
| invalid-armv8.1a.txt | ||
| invalid-armv8.txt | ||
| invalid-because-armv7.txt | ||
| invalid-thumb-MSR-MClass.txt | ||
| invalid-thumbv7-xfail.txt | ||
| invalid-thumbv7.txt | ||
| invalid-thumbv8.1a.txt | ||
| invalid-thumbv8.txt | ||
| invalid-virtexts.arm.txt | ||
| ldrd-armv4.txt | ||
| lit.local.cfg | ||
| load-store-acquire-release-v8-thumb.txt | ||
| load-store-acquire-release-v8.txt | ||
| marked-up-thumb.txt | ||
| memory-arm-instructions.txt | ||
| move-banked-regs-arm.txt | ||
| move-banked-regs-thumb.txt | ||
| mve-bitops.txt | ||
| mve-float.txt | ||
| mve-integer.txt | ||
| mve-interleave.txt | ||
| mve-load-store.txt | ||
| mve-lol.txt | ||
| mve-minmax.txt | ||
| mve-misc.txt | ||
| mve-qdest-qsrc.txt | ||
| mve-qdest-rsrc.txt | ||
| mve-reductions.txt | ||
| mve-scalar-shift-unpredictable.txt | ||
| mve-scalar-shift.txt | ||
| mve-shifts.txt | ||
| mve-vcmp.txt | ||
| mve-vmov-lane.txt | ||
| mve-vmov-pair.txt | ||
| mve-vpt.txt | ||
| neon-complex-arm.txt | ||
| neon-complex-thumb.txt | ||
| neon-crypto.txt | ||
| neon-tests.txt | ||
| neon-v8.txt | ||
| neon.txt | ||
| neont-VLD-reencoding.txt | ||
| neont-VST-reencoding.txt | ||
| neont2.txt | ||
| ras-extension-arm.txt | ||
| ras-extension-thumb.txt | ||
| thumb-MSR-MClass.txt | ||
| thumb-fp-armv8.txt | ||
| thumb-neon-crypto.txt | ||
| thumb-neon-v8.txt | ||
| thumb-printf.txt | ||
| thumb-tests.txt | ||
| thumb-v8.1a.txt | ||
| thumb-v8.txt | ||
| thumb-vmrs_vmsr.txt | ||
| thumb1.txt | ||
| thumb2-bit-15.txt | ||
| thumb2-preloads.txt | ||
| thumb2-v8.1m.txt | ||
| thumb2-v8.txt | ||
| thumb2-v8m.txt | ||
| thumb2.txt | ||
| thumbv8.1m-vmrs-vmsr.txt | ||
| thumbv8.1m.s | ||
| unpredictable-ADC-arm.txt | ||
| unpredictable-ADDREXT3-arm.txt | ||
| unpredictable-AExtI-arm.txt | ||
| unpredictable-AI1cmp-arm.txt | ||
| unpredictable-BFI.txt | ||
| unpredictable-LDR-arm.txt | ||
| unpredictable-LDRD-arm.txt | ||
| unpredictable-LSL-regform.txt | ||
| unpredictable-MRRC2-arm.txt | ||
| unpredictable-MRS-arm.txt | ||
| unpredictable-MUL-arm.txt | ||
| unpredictable-MVN-arm.txt | ||
| unpredictable-RSC-arm.txt | ||
| unpredictable-SEL-arm.txt | ||
| unpredictable-SHADD16-arm.txt | ||
| unpredictable-SSAT-arm.txt | ||
| unpredictable-STRBrs-arm.txt | ||
| unpredictable-UQADD8-arm.txt | ||
| unpredictable-swp-arm.txt | ||
| unpredictables-thumb.txt | ||
| vfp4.txt | ||
| virtexts-arm.txt | ||
| virtexts-thumb.txt | ||
| vmrs-vmsr-invalid.txt | ||
| vscclrm.txt | ||
| vstrldr_sys.txt | ||