forked from OSchip/llvm-project
39 lines
1.2 KiB
TableGen
39 lines
1.2 KiB
TableGen
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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// Minimal Target definition
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def DemoInstrInfo : InstrInfo;
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def Demo : Target {
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let InstructionSet = DemoInstrInfo;
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}
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// Some registers which can hold ints or floats
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foreach i = 0-7 in
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def "R" # i: Register<"r" # i>;
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def GPR : RegisterClass<"Demo", [i32, f32], 32, (sequence "R%u", 0, 7)>;
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// Instruction to convert an int to a float
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def i2f : Instruction {
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let Size = 2;
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let OutOperandList = (outs GPR:$dst);
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let InOperandList = (ins GPR:$src);
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let AsmString = "i2f $dst, $src";
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}
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// Some kind of special type-conversion node supported by this target
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def specialconvert : SDNode<"TEST_TARGET_ISD::SPECIAL_CONVERT", SDTUnaryOp>;
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// A PatFrags that matches either bitconvert or the special version
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def anyconvert : PatFrags<(ops node:$src),
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[(bitconvert node:$src),
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(specialconvert node:$src)]>;
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// And a rule that matches that PatFrag and turns it into i2f
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def : Pat<(f32 (anyconvert (i32 GPR:$val))), (i2f GPR:$val)>;
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// CHECK: SwitchOpcode{{.*}}ISD::BITCAST
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// CHECK: MorphNodeTo1{{.*}}i2f
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// CHECK: SwitchOpcode{{.*}}TEST_TARGET_ISD::SPECIAL_CONVERT
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// CHECK: MorphNodeTo1{{.*}}i2f
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