forked from OSchip/llvm-project
399 lines
13 KiB
C++
399 lines
13 KiB
C++
//===-- MCInstrDescView.cpp -------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCInstrDescView.h"
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#include <iterator>
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#include <map>
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#include <tuple>
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#include "llvm/ADT/STLExtras.h"
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namespace llvm {
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namespace exegesis {
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unsigned Variable::getIndex() const { return *Index; }
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unsigned Variable::getPrimaryOperandIndex() const {
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assert(!TiedOperands.empty());
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return TiedOperands[0];
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}
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bool Variable::hasTiedOperands() const {
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assert(TiedOperands.size() <= 2 &&
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"No more than two operands can be tied together");
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// By definition only Use and Def operands can be tied together.
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// TiedOperands[0] is the Def operand (LLVM stores defs first).
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// TiedOperands[1] is the Use operand.
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return TiedOperands.size() > 1;
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}
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unsigned Operand::getIndex() const { return *Index; }
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bool Operand::isExplicit() const { return Info; }
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bool Operand::isImplicit() const { return !Info; }
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bool Operand::isImplicitReg() const { return ImplicitReg; }
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bool Operand::isDef() const { return IsDef; }
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bool Operand::isUse() const { return !IsDef; }
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bool Operand::isReg() const { return Tracker; }
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bool Operand::isTied() const { return TiedToIndex.hasValue(); }
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bool Operand::isVariable() const { return VariableIndex.hasValue(); }
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bool Operand::isMemory() const {
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return isExplicit() &&
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getExplicitOperandInfo().OperandType == MCOI::OPERAND_MEMORY;
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}
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bool Operand::isImmediate() const {
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return isExplicit() &&
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getExplicitOperandInfo().OperandType == MCOI::OPERAND_IMMEDIATE;
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}
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unsigned Operand::getTiedToIndex() const { return *TiedToIndex; }
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unsigned Operand::getVariableIndex() const { return *VariableIndex; }
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unsigned Operand::getImplicitReg() const {
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assert(ImplicitReg);
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return *ImplicitReg;
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}
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const RegisterAliasingTracker &Operand::getRegisterAliasing() const {
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assert(Tracker);
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return *Tracker;
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}
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const MCOperandInfo &Operand::getExplicitOperandInfo() const {
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assert(Info);
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return *Info;
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}
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const BitVector *BitVectorCache::getUnique(BitVector &&BV) const {
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for (const auto &Entry : Cache)
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if (*Entry == BV)
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return Entry.get();
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Cache.push_back(std::make_unique<BitVector>());
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auto &Entry = Cache.back();
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Entry->swap(BV);
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return Entry.get();
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}
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Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
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SmallVector<Operand, 8> Operands,
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SmallVector<Variable, 4> Variables,
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const BitVector *ImplDefRegs,
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const BitVector *ImplUseRegs,
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const BitVector *AllDefRegs,
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const BitVector *AllUseRegs)
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: Description(*Description), Name(Name), Operands(std::move(Operands)),
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Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
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ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
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AllUseRegs(*AllUseRegs) {}
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std::unique_ptr<Instruction>
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Instruction::create(const MCInstrInfo &InstrInfo,
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const RegisterAliasingTrackerCache &RATC,
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const BitVectorCache &BVC, unsigned Opcode) {
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const llvm::MCInstrDesc *const Description = &InstrInfo.get(Opcode);
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unsigned OpIndex = 0;
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SmallVector<Operand, 8> Operands;
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SmallVector<Variable, 4> Variables;
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for (; OpIndex < Description->getNumOperands(); ++OpIndex) {
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const auto &OpInfo = Description->opInfo_begin()[OpIndex];
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Operand Operand;
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Operand.Index = OpIndex;
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Operand.IsDef = (OpIndex < Description->getNumDefs());
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// TODO(gchatelet): Handle isLookupPtrRegClass.
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if (OpInfo.RegClass >= 0)
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Operand.Tracker = &RATC.getRegisterClass(OpInfo.RegClass);
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int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO);
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assert((TiedToIndex == -1 ||
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(0 <= TiedToIndex &&
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TiedToIndex < std::numeric_limits<uint8_t>::max())) &&
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"Unknown Operand Constraint");
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if (TiedToIndex >= 0)
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Operand.TiedToIndex = TiedToIndex;
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Operand.Info = &OpInfo;
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Operands.push_back(Operand);
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}
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for (const MCPhysReg *MCPhysReg = Description->getImplicitDefs();
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MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
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Operand Operand;
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Operand.Index = OpIndex;
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Operand.IsDef = true;
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Operand.Tracker = &RATC.getRegister(*MCPhysReg);
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Operand.ImplicitReg = MCPhysReg;
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Operands.push_back(Operand);
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}
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for (const MCPhysReg *MCPhysReg = Description->getImplicitUses();
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MCPhysReg && *MCPhysReg; ++MCPhysReg, ++OpIndex) {
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Operand Operand;
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Operand.Index = OpIndex;
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Operand.IsDef = false;
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Operand.Tracker = &RATC.getRegister(*MCPhysReg);
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Operand.ImplicitReg = MCPhysReg;
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Operands.push_back(Operand);
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}
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Variables.reserve(Operands.size()); // Variables.size() <= Operands.size()
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// Assigning Variables to non tied explicit operands.
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for (auto &Op : Operands)
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if (Op.isExplicit() && !Op.isTied()) {
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const size_t VariableIndex = Variables.size();
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assert(VariableIndex < std::numeric_limits<uint8_t>::max());
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Op.VariableIndex = VariableIndex;
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Variables.emplace_back();
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Variables.back().Index = VariableIndex;
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}
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// Assigning Variables to tied operands.
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for (auto &Op : Operands)
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if (Op.isExplicit() && Op.isTied())
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Op.VariableIndex = Operands[Op.getTiedToIndex()].getVariableIndex();
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// Assigning Operands to Variables.
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for (auto &Op : Operands)
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if (Op.isVariable())
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Variables[Op.getVariableIndex()].TiedOperands.push_back(Op.getIndex());
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// Processing Aliasing.
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BitVector ImplDefRegs = RATC.emptyRegisters();
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BitVector ImplUseRegs = RATC.emptyRegisters();
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BitVector AllDefRegs = RATC.emptyRegisters();
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BitVector AllUseRegs = RATC.emptyRegisters();
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for (const auto &Op : Operands) {
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if (Op.isReg()) {
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const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
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if (Op.isDef())
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AllDefRegs |= AliasingBits;
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if (Op.isUse())
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AllUseRegs |= AliasingBits;
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if (Op.isDef() && Op.isImplicit())
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ImplDefRegs |= AliasingBits;
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if (Op.isUse() && Op.isImplicit())
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ImplUseRegs |= AliasingBits;
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}
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}
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// Can't use make_unique because constructor is private.
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return std::unique_ptr<Instruction>(new Instruction(
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Description, InstrInfo.getName(Opcode), std::move(Operands),
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std::move(Variables), BVC.getUnique(std::move(ImplDefRegs)),
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BVC.getUnique(std::move(ImplUseRegs)),
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BVC.getUnique(std::move(AllDefRegs)),
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BVC.getUnique(std::move(AllUseRegs))));
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}
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const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
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const auto PrimaryOperandIndex = Var.getPrimaryOperandIndex();
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assert(PrimaryOperandIndex < Operands.size());
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return Operands[PrimaryOperandIndex];
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}
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bool Instruction::hasMemoryOperands() const {
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return any_of(Operands, [](const Operand &Op) {
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return Op.isReg() && Op.isExplicit() && Op.isMemory();
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});
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}
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bool Instruction::hasAliasingImplicitRegisters() const {
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return ImplDefRegs.anyCommon(ImplUseRegs);
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}
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// Returns true if there are registers that are both in `A` and `B` but not in
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// `Forbidden`.
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static bool anyCommonExcludingForbidden(const BitVector &A, const BitVector &B,
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const BitVector &Forbidden) {
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assert(A.size() == B.size() && B.size() == Forbidden.size());
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const auto Size = A.size();
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for (int AIndex = A.find_first(); AIndex != -1;) {
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const int BIndex = B.find_first_in(AIndex, Size);
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if (BIndex == -1)
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return false;
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if (AIndex == BIndex && !Forbidden.test(AIndex))
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return true;
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AIndex = A.find_first_in(BIndex + 1, Size);
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}
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return false;
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}
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bool Instruction::hasAliasingRegistersThrough(
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const Instruction &OtherInstr, const BitVector &ForbiddenRegisters) const {
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return anyCommonExcludingForbidden(AllDefRegs, OtherInstr.AllUseRegs,
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ForbiddenRegisters) &&
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anyCommonExcludingForbidden(OtherInstr.AllDefRegs, AllUseRegs,
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ForbiddenRegisters);
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}
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bool Instruction::hasTiedRegisters() const {
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return any_of(Variables,
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[](const Variable &Var) { return Var.hasTiedOperands(); });
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}
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bool Instruction::hasAliasingRegisters(
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const BitVector &ForbiddenRegisters) const {
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return anyCommonExcludingForbidden(AllDefRegs, AllUseRegs,
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ForbiddenRegisters);
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}
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bool Instruction::hasOneUseOrOneDef() const {
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return AllDefRegs.count() || AllUseRegs.count();
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}
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void Instruction::dump(const MCRegisterInfo &RegInfo,
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const RegisterAliasingTrackerCache &RATC,
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raw_ostream &Stream) const {
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Stream << "- " << Name << "\n";
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for (const auto &Op : Operands) {
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Stream << "- Op" << Op.getIndex();
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if (Op.isExplicit())
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Stream << " Explicit";
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if (Op.isImplicit())
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Stream << " Implicit";
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if (Op.isUse())
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Stream << " Use";
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if (Op.isDef())
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Stream << " Def";
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if (Op.isImmediate())
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Stream << " Immediate";
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if (Op.isMemory())
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Stream << " Memory";
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if (Op.isReg()) {
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if (Op.isImplicitReg())
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Stream << " Reg(" << RegInfo.getName(Op.getImplicitReg()) << ")";
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else
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Stream << " RegClass("
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<< RegInfo.getRegClassName(
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&RegInfo.getRegClass(Op.Info->RegClass))
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<< ")";
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}
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if (Op.isTied())
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Stream << " TiedToOp" << Op.getTiedToIndex();
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Stream << "\n";
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}
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for (const auto &Var : Variables) {
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Stream << "- Var" << Var.getIndex();
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Stream << " [";
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bool IsFirst = true;
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for (auto OperandIndex : Var.TiedOperands) {
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if (!IsFirst)
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Stream << ",";
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Stream << "Op" << OperandIndex;
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IsFirst = false;
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}
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Stream << "]";
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Stream << "\n";
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}
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if (hasMemoryOperands())
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Stream << "- hasMemoryOperands\n";
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if (hasAliasingImplicitRegisters())
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Stream << "- hasAliasingImplicitRegisters (execution is always serial)\n";
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if (hasTiedRegisters())
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Stream << "- hasTiedRegisters (execution is always serial)\n";
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if (hasAliasingRegisters(RATC.emptyRegisters()))
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Stream << "- hasAliasingRegisters\n";
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}
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InstructionsCache::InstructionsCache(const MCInstrInfo &InstrInfo,
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const RegisterAliasingTrackerCache &RATC)
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: InstrInfo(InstrInfo), RATC(RATC), BVC() {}
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const Instruction &InstructionsCache::getInstr(unsigned Opcode) const {
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auto &Found = Instructions[Opcode];
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if (!Found)
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Found = Instruction::create(InstrInfo, RATC, BVC, Opcode);
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return *Found;
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}
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bool RegisterOperandAssignment::
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operator==(const RegisterOperandAssignment &Other) const {
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return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
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}
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bool AliasingRegisterOperands::
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operator==(const AliasingRegisterOperands &Other) const {
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return std::tie(Defs, Uses) == std::tie(Other.Defs, Other.Uses);
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}
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static void
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addOperandIfAlias(const MCPhysReg Reg, bool SelectDef,
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ArrayRef<Operand> Operands,
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SmallVectorImpl<RegisterOperandAssignment> &OperandValues) {
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for (const auto &Op : Operands) {
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if (Op.isReg() && Op.isDef() == SelectDef) {
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const int SourceReg = Op.getRegisterAliasing().getOrigin(Reg);
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if (SourceReg >= 0)
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OperandValues.emplace_back(&Op, SourceReg);
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}
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}
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}
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bool AliasingRegisterOperands::hasImplicitAliasing() const {
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const auto HasImplicit = [](const RegisterOperandAssignment &ROV) {
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return ROV.Op->isImplicit();
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};
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return any_of(Defs, HasImplicit) && any_of(Uses, HasImplicit);
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}
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bool AliasingConfigurations::empty() const { return Configurations.empty(); }
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bool AliasingConfigurations::hasImplicitAliasing() const {
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return any_of(Configurations, [](const AliasingRegisterOperands &ARO) {
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return ARO.hasImplicitAliasing();
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});
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}
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AliasingConfigurations::AliasingConfigurations(
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const Instruction &DefInstruction, const Instruction &UseInstruction) {
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if (UseInstruction.AllUseRegs.anyCommon(DefInstruction.AllDefRegs)) {
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auto CommonRegisters = UseInstruction.AllUseRegs;
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CommonRegisters &= DefInstruction.AllDefRegs;
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for (const MCPhysReg Reg : CommonRegisters.set_bits()) {
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AliasingRegisterOperands ARO;
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addOperandIfAlias(Reg, true, DefInstruction.Operands, ARO.Defs);
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addOperandIfAlias(Reg, false, UseInstruction.Operands, ARO.Uses);
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if (!ARO.Defs.empty() && !ARO.Uses.empty() &&
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!is_contained(Configurations, ARO))
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Configurations.push_back(std::move(ARO));
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}
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}
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}
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void DumpMCOperand(const MCRegisterInfo &MCRegisterInfo, const MCOperand &Op,
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raw_ostream &OS) {
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if (!Op.isValid())
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OS << "Invalid";
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else if (Op.isReg())
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OS << MCRegisterInfo.getName(Op.getReg());
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else if (Op.isImm())
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OS << Op.getImm();
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else if (Op.isFPImm())
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OS << Op.getFPImm();
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else if (Op.isExpr())
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OS << "Expr";
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else if (Op.isInst())
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OS << "SubInst";
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}
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void DumpMCInst(const MCRegisterInfo &MCRegisterInfo,
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const MCInstrInfo &MCInstrInfo, const MCInst &MCInst,
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raw_ostream &OS) {
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OS << MCInstrInfo.getName(MCInst.getOpcode());
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for (unsigned I = 0, E = MCInst.getNumOperands(); I < E; ++I) {
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if (I > 0)
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OS << ',';
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OS << ' ';
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DumpMCOperand(MCRegisterInfo, MCInst.getOperand(I), OS);
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}
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}
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} // namespace exegesis
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} // namespace llvm
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