forked from OSchip/llvm-project
190 lines
7.5 KiB
C++
190 lines
7.5 KiB
C++
//===--------------------- TimelineView.h -----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \brief
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///
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/// This file implements a timeline view for the llvm-mca tool.
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///
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/// Class TimelineView observes events generated by the pipeline. For every
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/// instruction executed by the pipeline, it stores information related to
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/// state transition. It then plots that information in the form of a table
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/// as reported by the example below:
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///
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/// Timeline view:
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/// 0123456
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/// Index 0123456789
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///
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/// [0,0] DeER . . .. vmovshdup %xmm0, %xmm1
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/// [0,1] DeER . . .. vpermilpd $1, %xmm0, %xmm2
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/// [0,2] .DeER. . .. vpermilps $231, %xmm0, %xmm5
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/// [0,3] .DeeeER . .. vaddss %xmm1, %xmm0, %xmm3
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/// [0,4] . D==eeeER. .. vaddss %xmm3, %xmm2, %xmm4
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/// [0,5] . D=====eeeER .. vaddss %xmm4, %xmm5, %xmm6
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///
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/// [1,0] . DeE------R .. vmovshdup %xmm0, %xmm1
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/// [1,1] . DeE------R .. vpermilpd $1, %xmm0, %xmm2
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/// [1,2] . DeE-----R .. vpermilps $231, %xmm0, %xmm5
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/// [1,3] . D=eeeE--R .. vaddss %xmm1, %xmm0, %xmm3
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/// [1,4] . D===eeeER .. vaddss %xmm3, %xmm2, %xmm4
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/// [1,5] . D======eeeER vaddss %xmm4, %xmm5, %xmm6
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///
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/// There is an entry for every instruction in the input assembly sequence.
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/// The first field is a pair of numbers obtained from the instruction index.
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/// The first element of the pair is the iteration index, while the second
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/// element of the pair is a sequence number (i.e. a position in the assembly
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/// sequence).
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/// The second field of the table is the actual timeline information; each
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/// column is the information related to a specific cycle of execution.
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/// The timeline of an instruction is described by a sequence of character
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/// where each character represents the instruction state at a specific cycle.
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///
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/// Possible instruction states are:
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/// D: Instruction Dispatched
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/// e: Instruction Executing
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/// E: Instruction Executed (write-back stage)
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/// R: Instruction retired
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/// =: Instruction waiting in the Scheduler's queue
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/// -: Instruction executed, waiting to retire in order.
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///
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/// dots ('.') and empty spaces are cycles where the instruction is not
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/// in-flight.
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///
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/// The last column is the assembly instruction associated to the entry.
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///
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/// Based on the timeline view information from the example, instruction 0
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/// at iteration 0 was dispatched at cycle 0, and was retired at cycle 3.
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/// Instruction [0,1] was also dispatched at cycle 0, and it retired at
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/// the same cycle than instruction [0,0].
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/// Instruction [0,4] has been dispatched at cycle 2. However, it had to
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/// wait for two cycles before being issued. That is because operands
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/// became ready only at cycle 5.
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///
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/// This view helps further understanding bottlenecks and the impact of
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/// resource pressure on the code.
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///
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/// To better understand why instructions had to wait for multiple cycles in
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/// the scheduler's queue, class TimelineView also reports extra timing info
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/// in another table named "Average Wait times" (see example below).
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///
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///
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/// Average Wait times (based on the timeline view):
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/// [0]: Executions
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/// [1]: Average time spent waiting in a scheduler's queue
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/// [2]: Average time spent waiting in a scheduler's queue while ready
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/// [3]: Average time elapsed from WB until retire stage
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///
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/// [0] [1] [2] [3]
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/// 0. 2 1.0 1.0 3.0 vmovshdup %xmm0, %xmm1
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/// 1. 2 1.0 1.0 3.0 vpermilpd $1, %xmm0, %xmm2
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/// 2. 2 1.0 1.0 2.5 vpermilps $231, %xmm0, %xmm5
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/// 3. 2 1.5 0.5 1.0 vaddss %xmm1, %xmm0, %xmm3
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/// 4. 2 3.5 0.0 0.0 vaddss %xmm3, %xmm2, %xmm4
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/// 5. 2 6.5 0.0 0.0 vaddss %xmm4, %xmm5, %xmm6
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/// 2 2.4 0.6 1.6 <total>
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///
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/// By comparing column [2] with column [1], we get an idea about how many
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/// cycles were spent in the scheduler's queue due to data dependencies.
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///
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/// In this example, instruction 5 spent an average of ~6 cycles in the
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/// scheduler's queue. As soon as operands became ready, the instruction
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/// was immediately issued to the pipeline(s).
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/// That is expected because instruction 5 cannot transition to the "ready"
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/// state until %xmm4 is written by instruction 4.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_TIMELINEVIEW_H
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#define LLVM_TOOLS_LLVM_MCA_TIMELINEVIEW_H
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#include "Views/View.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstPrinter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/raw_ostream.h"
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namespace llvm {
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namespace mca {
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/// This class listens to instruction state transition events
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/// in order to construct a timeline information.
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///
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/// For every instruction executed by the Pipeline, this class constructs
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/// a TimelineViewEntry object. TimelineViewEntry objects are then used
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/// to print the timeline information, as well as the "average wait times"
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/// for every instruction in the input assembly sequence.
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class TimelineView : public View {
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const llvm::MCSubtargetInfo &STI;
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llvm::MCInstPrinter &MCIP;
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llvm::ArrayRef<llvm::MCInst> Source;
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unsigned CurrentCycle;
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unsigned MaxCycle;
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unsigned LastCycle;
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struct TimelineViewEntry {
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int CycleDispatched; // A negative value is an "invalid cycle".
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unsigned CycleReady;
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unsigned CycleIssued;
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unsigned CycleExecuted;
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unsigned CycleRetired;
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};
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std::vector<TimelineViewEntry> Timeline;
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struct WaitTimeEntry {
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unsigned CyclesSpentInSchedulerQueue;
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unsigned CyclesSpentInSQWhileReady;
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unsigned CyclesSpentAfterWBAndBeforeRetire;
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};
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std::vector<WaitTimeEntry> WaitTime;
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// This field is used to map instructions to buffered resources.
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// Elements of this vector are <resourceID, BufferSizer> pairs.
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std::vector<std::pair<unsigned, int>> UsedBuffer;
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void printTimelineViewEntry(llvm::formatted_raw_ostream &OS,
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const TimelineViewEntry &E, unsigned Iteration,
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unsigned SourceIndex) const;
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void printWaitTimeEntry(llvm::formatted_raw_ostream &OS,
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const WaitTimeEntry &E, unsigned Index,
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unsigned Executions) const;
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// Display characters for the TimelineView report output.
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struct DisplayChar {
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static const char Dispatched = 'D';
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static const char Executed = 'E';
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static const char Retired = 'R';
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static const char Waiting = '='; // Instruction is waiting in the scheduler.
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static const char Executing = 'e';
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static const char RetireLag = '-'; // The instruction is waiting to retire.
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};
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public:
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TimelineView(const llvm::MCSubtargetInfo &sti, llvm::MCInstPrinter &Printer,
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llvm::ArrayRef<llvm::MCInst> S, unsigned Iterations,
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unsigned Cycles);
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// Event handlers.
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void onCycleEnd() override { ++CurrentCycle; }
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void onEvent(const HWInstructionEvent &Event) override;
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void onReservedBuffers(const InstRef &IR,
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llvm::ArrayRef<unsigned> Buffers) override;
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// print functionalities.
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void printTimeline(llvm::raw_ostream &OS) const;
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void printAverageWaitTimes(llvm::raw_ostream &OS) const;
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void printView(llvm::raw_ostream &OS) const override {
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printTimeline(OS);
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printAverageWaitTimes(OS);
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}
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};
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} // namespace mca
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} // namespace llvm
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#endif
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