forked from OSchip/llvm-project
192 lines
6.0 KiB
C++
192 lines
6.0 KiB
C++
//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_ARMDefines_h_
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#define lldb_ARMDefines_h_
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#include <cassert>
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#include <cstdint>
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// Common definitions for the ARM/Thumb Instruction Set Architecture.
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namespace lldb_private {
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// ARM shifter types
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typedef enum {
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SRType_LSL,
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SRType_LSR,
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SRType_ASR,
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SRType_ROR,
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SRType_RRX,
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SRType_Invalid
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} ARM_ShifterType;
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// ARM conditions // Meaning (integer) Meaning (floating-point)
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// Condition flags
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#define COND_EQ \
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0x0 // Equal Equal Z == 1
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#define COND_NE \
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0x1 // Not equal Not equal, or unordered Z == 0
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#define COND_CS \
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0x2 // Carry set >, ==, or unordered C == 1
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#define COND_HS 0x2
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#define COND_CC \
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0x3 // Carry clear Less than C == 0
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#define COND_LO 0x3
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#define COND_MI \
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0x4 // Minus, negative Less than N == 1
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#define COND_PL \
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0x5 // Plus, positive or zero >, ==, or unordered N == 0
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#define COND_VS \
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0x6 // Overflow Unordered V == 1
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#define COND_VC \
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0x7 // No overflow Not unordered V == 0
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#define COND_HI \
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0x8 // Unsigned higher Greater than, or unordered C == 1 and Z ==
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// 0
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#define COND_LS \
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0x9 // Unsigned lower or same Less than or equal C == 0 or Z ==
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// 1
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#define COND_GE \
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0xA // Greater than or equal Greater than or equal N == V
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#define COND_LT \
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0xB // Less than Less than, or unordered N != V
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#define COND_GT \
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0xC // Greater than Greater than Z == 0 and N ==
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// V
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#define COND_LE \
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0xD // Less than or equal <, ==, or unordered Z == 1 or N !=
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// V
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#define COND_AL \
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0xE // Always (unconditional) Always (unconditional) Any
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#define COND_UNCOND 0xF
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static inline const char *ARMCondCodeToString(uint32_t CC) {
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switch (CC) {
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default:
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assert(0 && "Unknown condition code");
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case COND_EQ:
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return "eq";
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case COND_NE:
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return "ne";
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case COND_HS:
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return "hs";
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case COND_LO:
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return "lo";
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case COND_MI:
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return "mi";
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case COND_PL:
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return "pl";
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case COND_VS:
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return "vs";
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case COND_VC:
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return "vc";
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case COND_HI:
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return "hi";
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case COND_LS:
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return "ls";
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case COND_GE:
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return "ge";
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case COND_LT:
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return "lt";
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case COND_GT:
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return "gt";
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case COND_LE:
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return "le";
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case COND_AL:
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return "al";
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}
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}
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static inline bool ARMConditionPassed(const uint32_t condition,
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const uint32_t cpsr) {
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const uint32_t cpsr_n = (cpsr >> 31) & 1u; // Negative condition code flag
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const uint32_t cpsr_z = (cpsr >> 30) & 1u; // Zero condition code flag
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const uint32_t cpsr_c = (cpsr >> 29) & 1u; // Carry condition code flag
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const uint32_t cpsr_v = (cpsr >> 28) & 1u; // Overflow condition code flag
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switch (condition) {
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case COND_EQ:
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return (cpsr_z == 1);
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case COND_NE:
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return (cpsr_z == 0);
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case COND_CS:
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return (cpsr_c == 1);
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case COND_CC:
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return (cpsr_c == 0);
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case COND_MI:
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return (cpsr_n == 1);
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case COND_PL:
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return (cpsr_n == 0);
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case COND_VS:
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return (cpsr_v == 1);
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case COND_VC:
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return (cpsr_v == 0);
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case COND_HI:
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return ((cpsr_c == 1) && (cpsr_z == 0));
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case COND_LS:
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return ((cpsr_c == 0) || (cpsr_z == 1));
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case COND_GE:
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return (cpsr_n == cpsr_v);
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case COND_LT:
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return (cpsr_n != cpsr_v);
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case COND_GT:
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return ((cpsr_z == 0) && (cpsr_n == cpsr_v));
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case COND_LE:
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return ((cpsr_z == 1) || (cpsr_n != cpsr_v));
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case COND_AL:
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case COND_UNCOND:
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default:
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return true;
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}
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return false;
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}
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// Bit positions for CPSR
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#define CPSR_T_POS 5
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#define CPSR_F_POS 6
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#define CPSR_I_POS 7
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#define CPSR_A_POS 8
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#define CPSR_E_POS 9
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#define CPSR_J_POS 24
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#define CPSR_Q_POS 27
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#define CPSR_V_POS 28
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#define CPSR_C_POS 29
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#define CPSR_Z_POS 30
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#define CPSR_N_POS 31
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// CPSR mode definitions
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#define CPSR_MODE_USR 0x10u
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#define CPSR_MODE_FIQ 0x11u
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#define CPSR_MODE_IRQ 0x12u
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#define CPSR_MODE_SVC 0x13u
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#define CPSR_MODE_ABT 0x17u
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#define CPSR_MODE_UND 0x1bu
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#define CPSR_MODE_SYS 0x1fu
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// Masks for CPSR
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#define MASK_CPSR_MODE_MASK (0x0000001fu)
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#define MASK_CPSR_IT_MASK (0x0600fc00u)
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#define MASK_CPSR_T (1u << CPSR_T_POS)
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#define MASK_CPSR_F (1u << CPSR_F_POS)
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#define MASK_CPSR_I (1u << CPSR_I_POS)
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#define MASK_CPSR_A (1u << CPSR_A_POS)
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#define MASK_CPSR_E (1u << CPSR_E_POS)
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#define MASK_CPSR_GE_MASK (0x000f0000u)
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#define MASK_CPSR_J (1u << CPSR_J_POS)
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#define MASK_CPSR_Q (1u << CPSR_Q_POS)
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#define MASK_CPSR_V (1u << CPSR_V_POS)
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#define MASK_CPSR_C (1u << CPSR_C_POS)
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#define MASK_CPSR_Z (1u << CPSR_Z_POS)
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#define MASK_CPSR_N (1u << CPSR_N_POS)
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} // namespace lldb_private
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#endif // lldb_ARMDefines_h_
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