forked from OSchip/llvm-project
443 lines
15 KiB
C++
443 lines
15 KiB
C++
//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This file contains definition for AMDGPU ISA disassembler
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//
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//===----------------------------------------------------------------------===//
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// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
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#include "AMDGPUDisassembler.h"
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#include "AMDGPU.h"
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#include "AMDGPURegisterInfo.h"
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#include "SIDefines.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-disassembler"
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typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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inline static MCDisassembler::DecodeStatus
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addOperand(MCInst &Inst, const MCOperand& Opnd) {
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Inst.addOperand(Opnd);
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return Opnd.isValid() ?
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MCDisassembler::Success :
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MCDisassembler::SoftFail;
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}
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#define DECODE_OPERAND2(RegClass, DecName) \
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static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
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unsigned Imm, \
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uint64_t /*Addr*/, \
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const void *Decoder) { \
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auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
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return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \
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}
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#define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass)
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DECODE_OPERAND(VGPR_32)
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DECODE_OPERAND(VS_32)
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DECODE_OPERAND(VS_64)
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DECODE_OPERAND(VReg_64)
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DECODE_OPERAND(VReg_96)
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DECODE_OPERAND(VReg_128)
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DECODE_OPERAND(SReg_32)
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DECODE_OPERAND(SReg_32_XM0)
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DECODE_OPERAND(SReg_64)
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DECODE_OPERAND(SReg_128)
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DECODE_OPERAND(SReg_256)
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DECODE_OPERAND(SReg_512)
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenDisassemblerTables.inc"
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//===----------------------------------------------------------------------===//
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//
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//===----------------------------------------------------------------------===//
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template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
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assert(Bytes.size() >= sizeof(T));
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const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
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Bytes = Bytes.slice(sizeof(T));
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return Res;
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}
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DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
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MCInst &MI,
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uint64_t Inst,
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uint64_t Address) const {
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assert(MI.getOpcode() == 0);
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assert(MI.getNumOperands() == 0);
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MCInst TmpInst;
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const auto SavedBytes = Bytes;
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if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
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MI = TmpInst;
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return MCDisassembler::Success;
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}
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Bytes = SavedBytes;
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return MCDisassembler::Fail;
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}
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DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes_,
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uint64_t Address,
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raw_ostream &WS,
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raw_ostream &CS) const {
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CommentStream = &CS;
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// ToDo: AMDGPUDisassembler supports only VI ISA.
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assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
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const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size());
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Bytes = Bytes_.slice(0, MaxInstBytesNum);
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DecodeStatus Res = MCDisassembler::Fail;
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do {
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// ToDo: better to switch encoding length using some bit predicate
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// but it is unknown yet, so try all we can
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// Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
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// encodings
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if (Bytes.size() >= 8) {
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const uint64_t QW = eatBytes<uint64_t>(Bytes);
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Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
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if (Res) break;
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Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
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if (Res) break;
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}
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// Reinitialize Bytes as DPP64 could have eaten too much
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Bytes = Bytes_.slice(0, MaxInstBytesNum);
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// Try decode 32-bit instruction
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if (Bytes.size() < 4) break;
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const uint32_t DW = eatBytes<uint32_t>(Bytes);
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Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address);
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if (Res) break;
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Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
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if (Res) break;
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if (Bytes.size() < 4) break;
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const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
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Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address);
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if (Res) break;
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Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
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} while (false);
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Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
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return Res;
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}
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const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
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return getContext().getRegisterInfo()->
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getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
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}
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inline
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MCOperand AMDGPUDisassembler::errOperand(unsigned V,
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const Twine& ErrMsg) const {
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*CommentStream << "Error: " + ErrMsg;
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// ToDo: add support for error operands to MCInst.h
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// return MCOperand::createError(V);
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return MCOperand();
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}
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inline
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MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
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return MCOperand::createReg(RegId);
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}
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inline
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MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
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unsigned Val) const {
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const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
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if (Val >= RegCl.getNumRegs())
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return errOperand(Val, Twine(getRegClassName(RegClassID)) +
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": unknown register " + Twine(Val));
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return createRegOperand(RegCl.getRegister(Val));
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}
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inline
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MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
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unsigned Val) const {
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// ToDo: SI/CI have 104 SGPRs, VI - 102
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// Valery: here we accepting as much as we can, let assembler sort it out
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int shift = 0;
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switch (SRegClassID) {
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case AMDGPU::SGPR_32RegClassID:
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case AMDGPU::TTMP_32RegClassID:
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break;
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case AMDGPU::SGPR_64RegClassID:
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case AMDGPU::TTMP_64RegClassID:
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shift = 1;
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break;
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case AMDGPU::SGPR_128RegClassID:
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case AMDGPU::TTMP_128RegClassID:
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// ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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case AMDGPU::SReg_256RegClassID:
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// ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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case AMDGPU::SReg_512RegClassID:
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shift = 2;
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break;
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// ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
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// this bundle?
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default:
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assert(false);
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break;
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}
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if (Val % (1 << shift))
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*CommentStream << "Warning: " << getRegClassName(SRegClassID)
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<< ": scalar reg isn't aligned " << Val;
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return createRegOperand(SRegClassID, Val >> shift);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
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return decodeSrcOp(OPW32, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
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return decodeSrcOp(OPW64, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
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// Some instructions have operand restrictions beyond what the encoding
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// allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
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// high bit.
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Val &= 255;
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return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
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return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
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return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
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return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
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// table-gen generated disassembler doesn't care about operand types
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// leaving only registry class so SSrc_32 operand turns into SReg_32
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// and therefore we accept immediates and literals here as well
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return decodeSrcOp(OPW32, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const {
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// SReg_32_XM0 is SReg_32 without M0
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return decodeOperand_SReg_32(Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
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// see decodeOperand_SReg_32 comment
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return decodeSrcOp(OPW64, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
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return decodeSrcOp(OPW128, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
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return createSRegOperand(AMDGPU::SReg_256RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
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return createSRegOperand(AMDGPU::SReg_512RegClassID, Val);
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}
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MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
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// For now all literal constants are supposed to be unsigned integer
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// ToDo: deal with signed/unsigned 64-bit integer constants
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// ToDo: deal with float/double constants
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if (Bytes.size() < 4)
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return errOperand(0, "cannot read literal, inst bytes left " +
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Twine(Bytes.size()));
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return MCOperand::createImm(eatBytes<uint32_t>(Bytes));
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}
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MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
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using namespace AMDGPU::EncValues;
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assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
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return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
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(static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
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(INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
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// Cast prevents negative overflow.
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}
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MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) {
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assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
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&& Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
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// ToDo: case 248: 1/(2*PI) - is allowed only on VI
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// ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as
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// literal constant.
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float V = 0.0f;
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switch (Imm) {
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case 240: V = 0.5f; break;
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case 241: V = -0.5f; break;
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case 242: V = 1.0f; break;
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case 243: V = -1.0f; break;
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case 244: V = 2.0f; break;
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case 245: V = -2.0f; break;
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case 246: V = 4.0f; break;
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case 247: V = -4.0f; break;
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case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI)
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0x3e22f983 :
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0x3fc45f306dc9c882);
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default: break;
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}
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return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V));
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}
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unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
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using namespace AMDGPU;
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assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
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switch (Width) {
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default: // fall
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case OPW32: return VGPR_32RegClassID;
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case OPW64: return VReg_64RegClassID;
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case OPW128: return VReg_128RegClassID;
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}
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}
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unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
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using namespace AMDGPU;
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assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
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switch (Width) {
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default: // fall
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case OPW32: return SGPR_32RegClassID;
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case OPW64: return SGPR_64RegClassID;
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case OPW128: return SGPR_128RegClassID;
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}
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}
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unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
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using namespace AMDGPU;
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assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
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switch (Width) {
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default: // fall
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case OPW32: return TTMP_32RegClassID;
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case OPW64: return TTMP_64RegClassID;
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case OPW128: return TTMP_128RegClassID;
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}
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}
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MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
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using namespace AMDGPU::EncValues;
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assert(Val < 512); // enum9
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if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
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return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
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}
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if (Val <= SGPR_MAX) {
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assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
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return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
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}
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if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
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return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
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}
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assert(Width == OPW32 || Width == OPW64);
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const bool Is32 = (Width == OPW32);
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if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
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return decodeIntImmed(Val);
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if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
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return decodeFPImmed(Is32, Val);
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if (Val == LITERAL_CONST)
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return decodeLiteralConstant();
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return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val);
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}
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MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
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using namespace AMDGPU;
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switch (Val) {
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case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
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case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
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// ToDo: no support for xnack_mask_lo/_hi register
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case 104:
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case 105: break;
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case 106: return createRegOperand(VCC_LO);
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case 107: return createRegOperand(VCC_HI);
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case 108: return createRegOperand(TBA_LO);
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case 109: return createRegOperand(TBA_HI);
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case 110: return createRegOperand(TMA_LO);
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case 111: return createRegOperand(TMA_HI);
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case 124: return createRegOperand(M0);
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case 126: return createRegOperand(EXEC_LO);
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case 127: return createRegOperand(EXEC_HI);
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// ToDo: no support for vccz register
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case 251: break;
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// ToDo: no support for execz register
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case 252: break;
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case 253: return createRegOperand(SCC);
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default: break;
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}
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return errOperand(Val, "unknown operand encoding " + Twine(Val));
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}
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MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
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using namespace AMDGPU;
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switch (Val) {
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case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
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case 106: return createRegOperand(VCC);
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case 108: return createRegOperand(TBA);
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case 110: return createRegOperand(TMA);
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case 126: return createRegOperand(EXEC);
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default: break;
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}
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return errOperand(Val, "unknown operand encoding " + Twine(Val));
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}
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static MCDisassembler *createAMDGPUDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new AMDGPUDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializeAMDGPUDisassembler() {
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TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
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}
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