forked from OSchip/llvm-project
121 lines
3.5 KiB
LLVM
121 lines
3.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s
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define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
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; CHECK-LABEL: test_vmovs_via_vext_lane0to0:
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%vec = insertelement <2 x float> %in, float %arg, i32 0
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%res = fadd <2 x float> %vec, %vec
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; CHECK: vext.32 d1, d1, d0, #1
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; CHECK: vext.32 d1, d1, d1, #1
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; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1
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ret <2 x float> %res
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}
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define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
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; CHECK-LABEL: test_vmovs_via_vext_lane0to1:
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%vec = insertelement <2 x float> %in, float %arg, i32 1
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%res = fadd <2 x float> %vec, %vec
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; CHECK: vext.32 d1, d1, d1, #1
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; CHECK: vext.32 d1, d1, d0, #1
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; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1
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ret <2 x float> %res
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}
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define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {
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; CHECK-LABEL: test_vmovs_via_vext_lane1to0:
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%vec = insertelement <2 x float> %in, float %arg, i32 0
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%res = fadd <2 x float> %vec, %vec
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; CHECK: vext.32 d1, d1, d1, #1
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; CHECK: vext.32 d1, d0, d1, #1
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; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1
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ret <2 x float> %res
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}
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define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {
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; CHECK-LABEL: test_vmovs_via_vext_lane1to1:
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%vec = insertelement <2 x float> %in, float %arg, i32 1
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%res = fadd <2 x float> %vec, %vec
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; CHECK: vext.32 d1, d0, d1, #1
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; CHECK: vext.32 d1, d1, d1, #1
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; CHECK: vadd.f32 {{d[0-9]+}}, d1, d1
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ret <2 x float> %res
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}
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define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {
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; CHECK-LABEL: test_vmovs_via_vdup:
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; Do an operation (which will end up NEON because of +neonfp) to convince the
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; execution-domain pass that NEON is a good thing to use.
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%res = fadd float %ret, %ret
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; It makes sense for LLVM to do the addition in d0 here, because it's going
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; to be returned. This means it will want a "vmov s0, s1":
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; CHECK: vdup.32 d0, d0[1]
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ret float %res
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}
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declare float @llvm.sqrt.f32(float)
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declare void @bar()
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; This is a comp
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define float @test_ineligible(float, float %in) {
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; CHECK-LABEL: test_ineligible:
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%sqrt = call float @llvm.sqrt.f32(float %in)
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%val = fadd float %sqrt, %sqrt
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; This call forces a move from a callee-saved register to the return-reg. That
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; move is not eligible for conversion to a d-register instructions because the
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; use-def chains would be messed up. Primarily a compile-test (we used to
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; internal fault).
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call void @bar()
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; CHECK: bl bar
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; CHECK: vext.32
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; CHECK: vext.32
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ret float %val
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}
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define i32 @test_vmovs_no_sreg(i32 %in) {
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; CHECK-LABEL: test_vmovs_no_sreg:
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; Check that the movement to and from GPRs takes place in the NEON domain.
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; CHECK: vmov.32 d
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%x = bitcast i32 %in to float
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%res = fadd float %x, %x
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; CHECK: vmov.32 r{{[0-9]+}}, d
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%resi = bitcast float %res to i32
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ret i32 %resi
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}
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; The point of this test is:
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; + Make sure s1 is live before the BL
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; + Make sure s1 is clobbered by the BL
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; + Convince LLVM to emit a VMOV to S0
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; + Convince LLVM to domain-convert this.
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; When all of those are satisfied, LLVM should *not* mark s1 as an implicit-use
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; because it's dead.
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declare float @clobbers_s1(float, float)
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define <2 x float> @test_clobbers_recognised(<2 x float> %invec, float %val) {
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%elt = call float @clobbers_s1(float %val, float %val)
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%vec = insertelement <2 x float> %invec, float %elt, i32 0
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%res = fadd <2 x float> %vec, %vec
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ret <2 x float> %res
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}
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