forked from OSchip/llvm-project
297 lines
12 KiB
C++
297 lines
12 KiB
C++
//===-- MipsFrameLowering.cpp - Mips Frame Information --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsFrameLowering.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsInstrInfo.h"
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#include "MipsMachineFunction.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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//
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// Stack Frame Processing methods
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// +----------------------------+
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//
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// The stack is allocated decrementing the stack pointer on
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// the first instruction of a function prologue. Once decremented,
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// all stack references are done thought a positive offset
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// from the stack/frame pointer, so the stack is considering
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// to grow up! Otherwise terrible hacks would have to be made
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// to get this stack ABI compliant :)
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//
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// The stack frame required by the ABI (after call):
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// Offset
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//
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// 0 ----------
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// 4 Args to pass
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// . saved $GP (used in PIC)
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// . Alloca allocations
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// . Local Area
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// . CPU "Callee Saved" Registers
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// . saved FP
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// . saved RA
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// . FPU "Callee Saved" Registers
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// StackSize -----------
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//
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// Offset - offset from sp after stack allocation on function prologue
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//
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// The sp is the stack pointer subtracted/added from the stack size
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// at the Prologue/Epilogue
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//
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// References to the previous stack (to obtain arguments) are done
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// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
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//
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// Examples:
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// - reference to the actual stack frame
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// for any local area var there is smt like : FI >= 0, StackOffset: 4
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// sw REGX, 4(SP)
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//
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// - reference to previous stack frame
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// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
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// The emitted instruction will be something like:
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// lw REGX, 16+StackSize(SP)
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//
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// Since the total stack size is unknown on LowerFormalArguments, all
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// stack references (ObjectOffset) created to reference the function
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// arguments, are negative numbers. This way, on eliminateFrameIndex it's
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// possible to detect those references and the offsets are adjusted to
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// their real location.
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//
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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bool MipsFrameLowering::hasFP(const MachineFunction &MF) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
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}
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bool MipsFrameLowering::targetHandlesStackFrameRounding() const {
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return true;
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}
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// Build an instruction sequence to load an immediate that is too large to fit
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// in 16-bit and add the result to Reg.
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static void expandLargeImm(unsigned Reg, int64_t Imm, bool IsN64,
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const MipsInstrInfo &TII, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator II, DebugLoc DL) {
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unsigned LUi = IsN64 ? Mips::LUi64 : Mips::LUi;
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unsigned ADDu = IsN64 ? Mips::DADDu : Mips::ADDu;
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unsigned ZEROReg = IsN64 ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ATReg = IsN64 ? Mips::AT_64 : Mips::AT;
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MipsAnalyzeImmediate AnalyzeImm;
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, IsN64 ? 64 : 32, false /* LastInstrIsADDiu */);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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// The first instruction can be a LUi, which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == LUi)
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BuildMI(MBB, II, DL, TII.get(LUi), ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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else
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ZEROReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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// Build the remaining instructions in Seq.
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for (++Inst; Inst != Seq.end(); ++Inst)
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BuildMI(MBB, II, DL, TII.get(Inst->Opc), ATReg).addReg(ATReg)
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.addImm(SignExtend64<16>(Inst->ImmOpnd));
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BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(Reg).addReg(ATReg);
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}
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void MipsFrameLowering::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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const MipsRegisterInfo *RegInfo =
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static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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// First, compute final stack size.
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unsigned StackAlign = getStackAlignment();
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uint64_t StackSize =
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RoundUpToAlignment(MipsFI->getMaxCallFrameSize(), StackAlign) +
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RoundUpToAlignment(MFI->getStackSize(), StackAlign);
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// Update stack size
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MFI->setStackSize(StackSize);
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI->adjustsStack()) return;
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MachineModuleInfo &MMI = MF.getMMI();
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std::vector<MachineMove> &Moves = MMI.getFrameMoves();
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MachineLocation DstML, SrcML;
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// Adjust stack.
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if (isInt<16>(-StackSize)) // addi sp, sp, (-stacksize)
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
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else { // Expand immediate that doesn't fit in 16-bit.
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MipsFI->setEmitNOAT();
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expandLargeImm(SP, -StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl);
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}
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// emit ".cfi_def_cfa_offset StackSize"
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MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
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DstML = MachineLocation(MachineLocation::VirtualFP);
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SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
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Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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if (CSI.size()) {
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// Find the instruction past the last instruction that saves a callee-saved
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// register to the stack.
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for (unsigned i = 0; i < CSI.size(); ++i)
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++MBBI;
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// Iterate over list of callee-saved registers and emit .cfi_offset
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// directives.
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MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
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for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
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E = CSI.end(); I != E; ++I) {
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int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
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unsigned Reg = I->getReg();
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// If Reg is a double precision register, emit two cfa_offsets,
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// one for each of the paired single precision registers.
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if (Mips::AFGR64RegClass.contains(Reg)) {
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const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg);
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MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
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MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
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MachineLocation SrcML0(*SubRegs);
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MachineLocation SrcML1(*(SubRegs + 1));
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if (!STI.isLittle())
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std::swap(SrcML0, SrcML1);
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Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
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Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
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} else {
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// Reg is either in CPURegs or FGR32.
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DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
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SrcML = MachineLocation(Reg);
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Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
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}
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
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// emit ".cfi_def_cfa_register $fp"
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MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
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BuildMI(MBB, MBBI, dl,
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TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
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DstML = MachineLocation(FP);
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SrcML = MachineLocation(MachineLocation::VirtualFP);
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Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
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}
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}
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void MipsFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const MipsInstrInfo &TII =
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*static_cast<const MipsInstrInfo*>(MF.getTarget().getInstrInfo());
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
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unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// Find the first instruction that restores a callee-saved register.
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MachineBasicBlock::iterator I = MBBI;
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for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i)
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--I;
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// Insert instruction "move $sp, $fp" at this location.
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BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
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}
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// Get the number of bytes from FrameInfo
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uint64_t StackSize = MFI->getStackSize();
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if (!StackSize)
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return;
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// Adjust stack.
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if (isInt<16>(StackSize)) // addi sp, sp, (-stacksize)
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BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
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else // Expand immediate that doesn't fit in 16-bit.
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expandLargeImm(SP, StackSize, STI.isABI_N64(), TII, MBB, MBBI, dl);
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}
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void MipsFrameLowering::
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processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const {
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MachineRegisterInfo& MRI = MF.getRegInfo();
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unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
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// FIXME: remove this code if register allocator can correctly mark
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// $fp and $ra used or unused.
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// Mark $fp and $ra as used or unused.
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if (hasFP(MF))
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MRI.setPhysRegUsed(FP);
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// The register allocator might determine $ra is used after seeing
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// instruction "jr $ra", but we do not want PrologEpilogInserter to insert
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// instructions to save/restore $ra unless there is a function call.
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// To correct this, $ra is explicitly marked unused if there is no
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// function call.
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if (MF.getFrameInfo()->hasCalls())
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MRI.setPhysRegUsed(Mips::RA);
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else {
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MRI.setPhysRegUnused(Mips::RA);
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MRI.setPhysRegUnused(Mips::RA_64);
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}
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}
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