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llvm-project/llvm/test/MC/Disassembler/Mips/mips32r6
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Vasileios Kalintiris 974d409259 [mips] Added support for the ERETNC instruction. 
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

llvm-svn: 242666
 		2015-07-20 12:28:56 +00:00
..
valid-mips32r6-el.txt [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. 2015-06-27 15:39:19 +00:00
valid-mips32r6.txt [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
valid-xfail-mips32r6.txt [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. 2015-01-29 11:33:41 +00:00